Nonvolatile Memory Hierarchical Bit Line Sequential Access
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Solution Overview
Problem
Current memory technologies, such as DRAM, are volatile and lose data when power is cut off, while next-generation nonvolatile memories like PCM, ReRAM, and MRAM face inefficiencies in data access and energy consumption during read operations.
Innovation Solution
A nonvolatile memory apparatus with a memory cell array and memory control circuit that uses a hierarchical bit line structure, allowing sequential data reading from multiple sub-arrays with a single read command signal, and includes a controller, column selecting circuit, and sense amplifiers to manage access and voltage for efficient data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a single read command signal is used to access multiple sub arrays sequentially, then energy efficiency is improved and page size is increased, but operation speed may be reduced due to sequential access
Solution Approach 1:
The memory system is divided into multiple sub arrays, each with its own bit lines connected to a shared global bit line through switching circuits. This segmentation allows independent access to different sub arrays while sharing common read/write pathways, improving energy efficiency by activating only necessary sub arrays and enhancing scalability.
Solution Approach 2:
The patent employs dynamic switching mechanisms that can rapidly connect or disconnect local bit lines to global bit lines based on access requirements. This dynamic reconfiguration enables the system to adapt between sequential access mode (for energy efficiency) and parallel access mode (for speed), resolving the contradiction between energy efficiency and operation speed.
2Device complexity
If multiple bit lines are coupled to a single global bit line through switching circuits, then device complexity is reduced and ease of operation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The switching circuits serve multiple functions: they act as connection switches between local and global bit lines, as selection mechanisms for different sub arrays, and as isolation elements to prevent signal interference. This multi-functionality reduces the need for separate dedicated circuits for each function, simplifying the overall device architecture despite the precision requirements.
Data Source
AI summary
A nonvolatile memory apparatus includes a memory cell array and a memory control circuit. The memory cell array includes a plurality of sub arrays each including a plurality of memory cells coupled to a plurality of bit lines. The memory control circuit sequentially couples thereto, based on a single read command signal, at least a single bit line disposed on the respective sub arrays to sequentially access a memory cell coupled to the at least single bit line.