Nonvolatile Memory Programming via Selective Bit Line Precharging
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Solution Overview
Problem
In multi-level cell flash memory devices, the separation of threshold voltage distributions for different states is challenging due to variations in response to verification voltage caused by the resistance of the common source line, leading to undesirably wide threshold voltage distributions and reduced sensing margins.
Innovation Solution
The method involves performing program loops with and without bitline precharging during program verification operations, activating precharging only when threshold voltages exceed a certain base voltage to minimize voltage rise and maintain accurate programming, thereby optimizing the programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bitline precharging is activated during all program verification operations, then sensing accuracy is improved, but voltage rise due to common source line resistance increases causing wider threshold voltage distributions
Solution Approach 1:
The patent dynamically adjusts the bitline precharging operation based on the program loop count. Precharging is activated only when the loop count exceeds a threshold value, rather than being statically enabled for all verification operations. This dynamic control allows the system to adapt to the changing electrical conditions during progressive programming, reducing voltage rise when it would be harmful while maintaining sensing accuracy when needed.
Solution Approach 2:
The patent changes the operational parameter of bitline precharging from a constant state to a conditional state based on program loop progress. By monitoring the loop count and comparing it to a threshold, the system modifies the precharging behavior to optimize both sensing accuracy and threshold voltage distribution width at different stages of the programming process.
2Manufacturing precision
If bitline precharging is inactivated during program verification operations, then voltage rise is reduced improving threshold voltage distribution, but sensing accuracy deteriorates
Solution Approach 1:
The system dynamically switches between precharging and non-precharging modes based on the program loop count threshold. This dynamic adjustment ensures that precharging is applied only when the programming progress justifies the benefit, balancing voltage distribution quality with sensing accuracy requirements throughout the programming sequence.
Solution Approach 2:
The operational parameter of bitline precharging is changed from a fixed state to a conditional state that varies with program loop count. This parameter change allows the system to optimize the trade-off between threshold voltage distribution width and sensing accuracy at different programming stages.
3Manufacturing precision
If program loops are increased to achieve better programming accuracy, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent applies partial precharging action rather than continuous precharging throughout all program loops. By activating precharging only when the loop count exceeds a threshold, the system performs the useful action of voltage stabilization only when necessary, reducing unnecessary time consumption while maintaining programming accuracy where it matters most.
Solution Approach 2:
The system skips the precharging operation during early program loops where it would be counterproductive, rushing through these initial stages without precharging to save time. Precharging is then applied in later loops where it provides genuine benefit to programming accuracy, effectively skipping unnecessary operations while maintaining quality.
Data Source
AI summary
A method of programming a nonvolatile memory device comprises programming memory cells by performing a plurality of program loops with bitline precharging inactivated during program verification operations of some of the program loops, and with bitline precharging activated during program verification operations of some of the program loops.