Nonvolatile Memory Bit-Line Layout for Uniform Read/Write Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High integration and increased speed requirements in nonvolatile memory devices lead to reduced time windows for operations, causing issues with data output speed differences and reliability.
Innovation Solution
The nonvolatile memory device includes a memory cell array with specific bit line and word line configurations, utilizing poly and metal lines connected by contacts to maintain uniform parasitic resistance and ensure consistent access times across bit lines, enhancing write and read reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high integration is implemented to reduce manufacturing costs and increase storage capacity, then storage capacity and integration density are improved, but parasitic resistance becomes non-uniform and reliability deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the configuration of bit lines based on their position relative to word lines. Specifically, bit lines are divided into first bit lines (adjacent to word lines) and second bit lines (not adjacent), with different connection structures to contacts. This localized differentiation ensures that bit lines experiencing higher parasitic resistance due to their position have enhanced compensation through alternative contact connections, thereby maintaining uniform access features and improving reliability while supporting high integration.
2Speed
If speed requirements are increased to meet performance demands, then operation speed is improved, but time window for operations decreases causing reliability issues
Solution Approach 1:
The patent applies parameter changes by modifying the electrical characteristics of bit lines through different contact connection configurations. By changing the connection parameters (which contacts bit lines connect to, and in what order), the patent compensates for position-dependent parasitic resistance variations. This ensures that bit lines at different positions have effectively equalized access resistance, maintaining uniform access times even at higher operating speeds, thus improving reliability without sacrificing speed performance.
3Stability of the object's composition
If bit lines are arranged in specific configurations to reduce parasitic resistance, then access uniformity is improved, but device structure becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing bit lines into distinct categories (first bit lines and second bit lines) based on their spatial relationship with word lines. This segmentation allows for differentiated contact connection strategies: first bit lines connect to specific contacts while second bit lines connect to other contacts. By segmenting the bit line array, the patent achieves uniform access features through targeted compensation without requiring complete redesign of the entire bit line structure, thus managing complexity effectively.
Data Source
AI summary
A memory device may include a memory cell array, and a write driver and sense amplifier connected to the memory cell array through bit lines. The memory cell array includes a first cell area including a plurality of first memory cells arranged on a plane corresponding to a first direction and a second direction, a second cell area including a plurality of second memory cells arranged on the plane disposed on one side of the first cell area in the first direction, a word line extending in the first direction and is connected to the plurality of first memory cells and the plurality of second memory cells, first bit lines extending in the second direction and are respectively connected to the plurality of first memory cells, and second bit lines extending in the second direction and are respectively connected to the plurality of second memory cells.