Nonvolatile Memory Block Decoders for Data Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High integration and reduced scale in semiconductor memory devices lead to reliability issues and data degradation, necessitating a method to enhance the reliability of nonvolatile memory and storage devices.
Innovation Solution
The implementation of a nonvolatile memory architecture with multiple memory blocks, pass transistors, block decoders, and pass transistor decoders that control voltages to improve access and reliability by floating word lines of unselected memory blocks, preventing data loss and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high integration and reduced scale are implemented in nonvolatile memory, then production cost is reduced and capacity is increased, but reliability is degraded and data loss occurs
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block, second memory block, third memory block, fourth memory block) grouped into memory block groups. Each block has dedicated decoders and pass transistor groups, allowing independent control and isolation of faults to specific segments, thereby improving overall reliability without requiring complete redesign of the entire memory structure.
Solution Approach 2:
Block pass transistors are introduced as intermediary components between block decoders and pass transistor groups. These intermediaries enable precise control of voltage signals to specific memory blocks, allowing the system to selectively activate or isolate blocks as needed, which enhances reliability by preventing data loss from unselected blocks while managing structural complexity through controlled signal routing.
2Reliability
If high integration is implemented, then production cost is reduced, but data loss from unselected memory blocks occurs
Solution Approach 1:
The memory structure is segmented into multiple independently controllable blocks with dedicated decoders and pass transistor groups. This segmentation allows manufacturing processes to target specific blocks or groups, simplifying quality control and defect isolation during manufacturing while ensuring data integrity through selective activation of only required memory blocks.
Solution Approach 2:
Different memory blocks and groups are equipped with dedicated control circuits (block decoders, pass transistor groups) that provide localized control. This local quality approach ensures that each block can be independently managed and protected, preventing data loss in unselected blocks while maintaining manufacturing efficiency through modular assembly and testing procedures.
3Speed
If multiple memory blocks are accessed simultaneously, then access speed is improved, but voltage control complexity increases
Solution Approach 1:
The voltage control system is segmented into multiple independent block decoders and pass transistor groups, each responsible for specific memory blocks. This segmentation allows simultaneous voltage control for multiple blocks without signal interference, improving access speed while managing control complexity through distributed control architecture where each decoder handles only its assigned blocks.
Solution Approach 2:
Block pass transistors serve as intermediary voltage control elements between block decoders and memory blocks. These intermediaries simplify voltage control by providing dedicated signal paths for each block group, enabling simultaneous access to multiple blocks while reducing control complexity through standardized voltage routing patterns and isolated control signals for each block group.
Data Source
AI summary
A nonvolatile memory includes a plurality of memory blocks, a plurality of source drivers corresponding to the plurality of memory blocks, a plurality of pass transistor groups connected between the plurality of source drivers and the plurality of memory blocks, a plurality of block pass transistors connected between a plurality of block word lines and the plurality of pass transistor groups, a plurality of block decoders corresponding to a plurality of memory block groups respectively, and a block pass transistor decoder configured to control voltages of block select lines connected to the plurality of block pass transistors. The plurality of memory blocks are divided into the plurality of memory block groups. Each block decoder is configured to control voltages of block word lines, among the plurality of block word lines, connected to at least two memory blocks of a corresponding memory block group in common.