Nonvolatile Memory Block Reuse with Read-Completion Counters
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Solution Overview
Problem
Existing nonvolatile memory systems face challenges in efficiently managing data reading and writing operations, particularly in NAND flash technologies, leading to conflicts between data reading and block reuse requests, which can result in data un-readability due to incomplete read commands and buffer region releases.
Innovation Solution
A memory system with a controller that manages counter values for blocks and buffers to ensure data readability by preventing blocks and buffers from being reused until all read commands are completed, thereby ensuring data can be correctly read from intended sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If blocks and buffers are reused quickly to improve productivity, then block reuse efficiency is improved, but data readability is compromised due to incomplete read commands
Solution Approach 1:
The controller performs preliminary actions by setting counter values for blocks and buffers before reuse operations. The counter value setting unit establishes initial counter values that indicate the number of read commands to be executed, preventing premature reuse of blocks and buffers until all read operations are completed. This preliminary action ensures data readability is maintained while enabling efficient block reuse management.
Solution Approach 2:
The system implements feedback mechanisms through counter values that are updated based on read command execution status. The counter value update unit monitors whether read commands are completed and adjusts counter values accordingly. When counter values reach zero (indicating all reads are complete), the blocks and buffers become available for reuse. This feedback loop resolves the contradiction by dynamically controlling reuse based on actual read completion status.
2Speed
If counter values are set to zero immediately after write operations, then block reuse speed is improved, but data un-readability occurs due to premature buffer release
Solution Approach 1:
Instead of setting counter values to zero immediately, the system performs a preliminary action by setting counter values based on the number of read commands that need to be executed. This preliminary counter value setting prevents premature buffer release and ensures data remains readable until all read operations are completed, while still enabling efficient reuse management once reads are finished.
Solution Approach 2:
The counter values serve as feedback indicators that reflect the actual status of read operations. The counter value update unit continuously monitors read command completion and updates counter values accordingly. This feedback mechanism prevents information loss by ensuring blocks and buffers are only reused when counter values indicate all read operations are complete, thus maintaining data readability while enabling fast reuse.
3Productivity
If multiple read commands are executed in parallel to improve productivity, then read throughput is improved, but block management complexity increases due to tracking multiple read operations
Solution Approach 1:
The system merges the tracking of multiple read operations into a unified counter value management mechanism. Instead of maintaining separate tracking structures for each read command, the counter value setting unit and update unit manage a single counter value that represents the total number of pending read commands for each block. This merging approach enables parallel read execution while simplifying block management complexity through unified counter-based tracking.
Data Source
AI summary
A memory system includes a nonvolatile memory including a plurality of blocks and a controller configured to write data to a plurality of write destination blocks allocated from the plurality of blocks. The controller is configured to in response to receiving a read command from a host, increment a first counter value corresponding to a first block having a block address allocated to a logical address of read target data specified by the received read command. The controller is configured to read the read target data from the first block or a buffer depending on whether the read target data is readable from the first block, and decrement the first counter value corresponding to the first block. The controller is configured to prohibit processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block.