Nonvolatile Memory Buffer Region Segmentation for Speed

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Solution Overview

Problem

The operating speed of flash memory in semiconductor devices is lower than the signal processing speed of host processors and interface signal transmission speeds, necessitating improvements to enhance performance and efficiency.

Innovation Solution

A nonvolatile memory device with a buffer region and a main region, where sub-page data is processed through pre-main, buffered, and re-main programming operations, allowing for efficient data storage and retrieval by optimizing programming operations based on bit ordering and threshold voltage distributions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If flash memory is used for nonvolatile storage, then data retention without power is achieved, but operating speed is lower than host processor and interface signal speeds

Engineering Contradiction:
Improvedata retentionVSAvoidoperating speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The memory device is divided into a buffer region and a main region. The buffer region uses memory cells with first threshold voltages for faster programming operations, while the main region uses memory cells with second threshold voltages for higher storage density. This segmentation allows the system to achieve both fast operating speeds (in buffer) and high capacity (in main), resolving the contradiction between speed and reliability.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If buffer region is used to store sub-page data, then programming flexibility is improved, but buffer region usage increases

Engineering Contradiction:
Improveprogramming flexibilityVSAvoidbuffer region usage
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The buffer region is used to preliminarily store sub-page data before the main programming operation is completed. This preliminary action allows the system to accept and buffer incoming data at high speeds without blocking the main programming operations, providing programming flexibility while minimizing the required buffer size by only storing what is temporarily needed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9785379B2Operating method of nonvolatile memory device and nonvolatile memory system
Publication Date: 2017.10.10 SAMSUNG ELECTRONICS CO LTD
  • US9785379B2 patent drawing
  • US9785379B2 patent drawing
  • US9785379B2 patent drawing

AI summary

An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation.