Nonvolatile Memory Request Scheduling by Chip Busy State

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Solution Overview

Problem

In memory systems with nonvolatile memory chips, inefficiencies arise when a large number of requests designate a single chip, leading to resource wastage and reduced throughput due to unprocessed commands.

Innovation Solution

A controller identifies nonvolatile memory chips that are not in a busy state and processes requests accordingly, managing busy states to optimize resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the memory system fetches a large number of requests designating a single nonvolatile memory chip, then the host can issue requests efficiently, but resources of the memory system are wasted and throughput is reduced due to inability to immediately start corresponding processes

Engineering Contradiction:

Improverequest issuance efficiencyVSAvoidprocessing throughput

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent segments the request processing by separating fetched requests into different queues based on the target nonvolatile memory chip's busy state. Requests for chips in busy state are placed in a waiting queue, while requests for idle chips are placed in an execution queue, allowing parallel processing and resource optimization

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The controller performs preliminary action by checking the busy state of nonvolatile memory chips before fetching requests and pre-organizing requests into appropriate queues. This preliminary classification prevents resource wastage by ensuring requests are only processed when the target chip is available

Inventive Principle:

Principle #10Preliminary action

2Speed

If requests are fetched without checking chip busy state, then request processing can start immediately, but resources are wasted on requests that cannot be immediately processed

Engineering Contradiction:

Improverequest processing speedVSAvoidresource wastage

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The system implements feedback by continuously monitoring the busy state of nonvolatile memory chips and using this information to dynamically adjust request fetching and queue management. The controller fetches requests based on real-time chip availability feedback, preventing resource wastage while maintaining processing speed

Inventive Principle:

Principle #23Feedback

3Adaptability or versatility

If the memory system processes requests for busy chips, then all fetched requests can be handled, but efficiency is reduced due to lack of available resources

Engineering Contradiction:

Improverequest handling capabilityVSAvoidprocess efficiency

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies dynamics by making the request processing system adaptive to changing chip states. The controller dynamically switches between processing requests from the execution queue when chips are idle and transferring requests from the waiting queue when chips become available, optimizing both adaptability and efficiency

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12443372B2Memory system and method of controlling memory chips

Publication Date: 2025.10.14 KIOXIA CORP

AI summary

According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.