Nonvolatile Memory Cache Control for SSD Garbage Collection
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Solution Overview
Problem
Current solid state drive (SSD) systems face inefficiencies in data management and garbage collection, leading to unnecessary writes and reduced lifespan of nonvolatile memory, as they lack effective mechanisms to differentiate between valid and invalid data and determine optimal erasure conditions for blocks.
Innovation Solution
The implementation of a cache control system that uses address translation, valid/invalid data identification, and garbage collection units to manage data in nonvolatile memory, allowing for selective writing and erasure of invalid data, and optimizing block usage based on access frequencies and FIFO principles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SSD garbage collection is used without valid/invalid data differentiation, then all data in selected blocks is erased regardless of validity, but this causes unnecessary writes and reduces memory lifespan
Solution Approach 1:
The system performs preliminary identification of valid and invalid data before erasure operations. By using valid/invalid flags and reference counting mechanisms, the SSD determines which data should be preserved and which can be erased, preventing unnecessary writes and extending memory lifespan while maintaining garbage collection efficiency
Solution Approach 2:
The system implements feedback mechanisms through reference counting and valid/invalid flag tracking. When data is marked for deletion, the reference count is decremented and the valid flag is set to invalid. The garbage collection unit continuously monitors these states and only erases blocks when reference counts reach zero, ensuring that valid data is preserved while efficiently removing invalid data
2Measurement precision
If address translation is implemented to track logical to physical addresses, then data management precision is improved, but device complexity increases
Solution Approach 1:
The address translation function is segmented into distinct components: a translation layer that maps logical addresses to physical addresses, and a valid/invalid flag management system. This segmentation allows precise address tracking while organizing the complexity into manageable, independent modules that can be operated separately
Solution Approach 2:
The patent introduces an intermediary address translation layer between the host and the physical memory blocks. This intermediary maintains the logical-to-physical mapping and valid/invalid status without requiring changes to the underlying memory structure, thereby improving address management precision while containing complexity within the translation layer
3Duration of action of stationary object
If selective erasure of invalid data is implemented, then memory lifespan is extended, but the complexity of determining erasure conditions increases
Solution Approach 1:
The system performs preliminary marking of invalid data using valid/invalid flags and reference counting before erasure. By pre-identifying which data can be safely erased, the system extends memory lifespan through selective erasure while keeping the erasure condition logic relatively simple - erasure occurs when reference count reaches zero and valid flag is false
Solution Approach 2:
The garbage collection system uses self-service mechanisms where the reference count and valid flag automatically track data status. When data is deleted, the reference count is automatically decremented. The erasure condition is self-determined when the reference count reaches zero, eliminating the need for complex external determination logic
Data Source
AI summary
According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.