3D Nonvolatile Memory Cell Array with Differential Word Line Groups
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Solution Overview
Problem
Current flash memory devices face limitations in storage capacity and integration due to their two-dimensional structure, necessitating the development of a nonvolatile memory device with a three-dimensional structure to enhance data storage capabilities.
Innovation Solution
The proposed nonvolatile memory device features a memory cell array with multiple cell strings stacked perpendicular to the substrate, where memory cells are arranged at intersections of word lines and bit lines, allowing for varying data bits storage across different word line groups, and a memory controller performs multi-dimensional modulation to optimize data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a two-dimensional structure is used in flash memory devices, then manufacturing and operation are simpler, but storage capacity and integration are limited
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional structure by stacking multiple memory cell layers vertically. Multiple bit lines extend through different layers, and word lines are arranged in upper and lower groups, creating a spatial hierarchy that dramatically increases storage capacity while maintaining manageable complexity through systematic organization
2Quantity of substance
If all memory cells store the same number of data bits, then operation is uniform and simple, but storage capacity cannot be optimized
Solution Approach 1:
The patent implements local quality by allowing different word line groups (upper and lower) to store different numbers of data bits. The controller dynamically determines which word line group stores how many bits based on the specific data being written, optimizing storage capacity for each local region rather than using a uniform approach across the entire memory array
3Quantity of substance
If non-integer data bits are stored in memory cells, then storage capacity is maximized, but error rates increase
Solution Approach 1:
The patent introduces a controller as an intermediary that manages the complexity of storing non-integer data bits. The controller performs multi-dimensional modulation to encode data across multiple memory cells, distributing the representation of fractional bits across cell groups. This intermediary layer handles the complexity of non-integer bit storage while maintaining reliability through systematic error management
Data Source
AI summary
A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.