Nonvolatile Memory Cell Array Bit Storage Optimization
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Solution Overview
Problem
Three-dimensional (3D) nonvolatile memory devices experience degradation in data retention due to stacking, leading to differences in threshold voltage distributions between outer and inner memory cells, affecting programming speeds and reliability.
Innovation Solution
A nonvolatile memory device with a memory cell array and control circuit that groups memory cells into outer and inner cells based on their distance from a word-line cut region, allowing for different bit storage capacities and adjusting read voltages to discriminate between threshold voltage distributions, thereby reducing degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in a three-dimensional configuration, then storage capacity is improved, but data retention characteristic deteriorates
Solution Approach 1:
The patent applies local quality by differentiating between outer memory cells and inner memory cells based on their positions relative to the word line cut region. Outer cells are programmed to store a first number of bits while inner cells store a second number of bits, with each region optimized for its specific retention characteristics. This localized differentiation allows the system to maintain high storage capacity through 3D stacking while preserving data retention reliability in critical regions.
2Productivity
If outer and inner memory cells are programmed with the same number of bits, then programming speed is improved, but data retention reliability deteriorates
Solution Approach 1:
The patent implements local quality by assigning different bit storage capacities to outer and inner memory cells based on their positional characteristics. Outer cells, being closer to the word line cut region, are programmed to store a first number of bits optimized for their retention characteristics, while inner cells store a second number of bits. This differentiated approach ensures that each cell region operates within its optimal performance parameters, balancing programming speed with data retention reliability.
3Measurement precision
If read voltages are adjusted to discriminate between threshold voltage distributions, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by adjusting read voltage levels to match the differentiated storage capacities of outer and inner memory cells. The control circuit is configured to apply first read voltages for outer cells and second read voltages for inner cells, where these voltage levels are optimized to discriminate between the threshold voltage distributions of the two cell types. This parameter differentiation enables precise data reading while maintaining manageable control circuit complexity through systematic voltage management.
Data Source
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AI summary
A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.