Non-Volatile Memory Cell Array Layout for Analog Synapse Weights
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Solution Overview
Problem
The development of artificial neural networks for high-performance information processing is hindered by a lack of adequate hardware technology, particularly in terms of energy efficiency and scalability of synapses in existing digital and analog systems.
Innovation Solution
A memory device utilizing a non-volatile memory array with a specific architecture that includes alternating source and drain regions, floating gates, and non-floating gates, allowing for continuous programming and precise tuning of synapse weights in neural networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent replaces digital mechanical computing systems with analog electrical circuits implemented in CMOS technology. The synapse weights are represented by continuous analog values stored in memory cells, and neural network computations are performed through analog matrix multiplication operations, eliminating the need for digital processing and significantly improving energy efficiency while maintaining high computational parallelism
Solution Approach 2:
The invention changes the parameter representation from discrete digital values to continuous analog values. Memory cell parameters such as resistance or capacitance are used to represent synapse weights, allowing for continuous tuning and storage of weight values. This parameter transformation enables efficient analog computation operations that consume much less energy than digital alternatives
2Use of energy by moving object
If CMOS analog circuits are used for artificial neural networks, then energy efficiency is improved, but device area increases due to bulky synapse implementations
Solution Approach 1:
The patent segments the synapse functionality into separate components: weight storage is implemented in non-volatile memory cells while the computational operations are performed by shared analog circuitry. This segmentation allows multiple synapses to share common readout and computation resources, dramatically reducing the area per synapse compared to fully dedicated implementations
Solution Approach 2:
The invention implements universal readout circuitry and computation units that can serve multiple synapses simultaneously. The analog matrix multiplication unit processes inputs from multiple memory cells through shared circuit paths, allowing the same hardware resources to be reused across many synapse operations, thereby reducing overall device area while maintaining energy efficiency
Data Source
AI summary
A memory device includes a non-volatile memory cells, source regions and drain regions arranged in rows and columns. Respective ones of the columns of drain regions include first drain regions and second drain regions that alternate with each other. Respective ones of first lines electrically connect together the source regions in one of the rows of the source regions and are electrically isolated from the source regions in other rows of the source regions. Respective ones of second lines electrically connect together the first drain regions of one of the columns of drain regions and are electrically isolated from the second drain regions of the one column of drain regions. Respective ones of third lines electrically connect together the second drain regions of one of the columns of drain regions and are electrically isolated from the first drain regions of the one column of drain regions.