Nonvolatile Memory Cell Architecture for Erase Disturb Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional nonvolatile memory arrays face issues with erase disturb and reliability due to the use of additional layers, which increase costs and production times, and result in reduced yield, as well as data disturbance during the erasing of selected memory cells.
Innovation Solution
A novel memory architecture with a nonvolatile memory array that orients erase lines differently and uses programming and erasing methods allowing charge carriers to tunnel through different dielectric layers within memory cells, reducing dielectric failure and data disturbance by maintaining unselected memory cells at voltages closer to each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional nonvolatile memory arrays use additional layers (floating gate electrode, control gate, nitride layer), then charge storage capability is improved, but manufacturing complexity and production time increase, and yield decreases
Solution Approach 1:
The patent extracts and eliminates the separate floating gate electrode and control gate layers from the memory cell structure. By removing these additional layers and using only a single gate electrode layer that serves both transistor and memory cell functions, the invention simplifies the manufacturing process while maintaining charge storage capability through alternative mechanisms (tunneling through oxide layers).
Solution Approach 2:
The single gate electrode layer performs multiple functions: it serves as the gate for the transistor in the logic block and simultaneously functions as the gate electrode for nonvolatile memory cells. This multi-functional approach eliminates the need for separate floating gate and control gate structures, reducing manufacturing complexity while maintaining memory functionality.
2Reliability
If conventional nonvolatile memory arrays use separate floating gate and control gate layers, then memory functionality is achieved, but production time increases
Solution Approach 1:
The patent merges the functions of the floating gate electrode and control gate into a single gate electrode layer. This consolidation allows the same layer to be used for both transistor operation and memory cell operation, eliminating the need for separate formation processes and reducing overall production time while maintaining nonvolatile memory functionality.
3Reliability
If conventional nonvolatile memory arrays use additional charge storage layers, then memory capacity is improved, but manufacturing yield decreases
Solution Approach 1:
The patent removes the additional charge storage layers (floating gate, control gate, nitride layer) from the conventional memory structure. By eliminating these complex multi-layer structures and using a simplified single-gate approach with tunneling mechanisms, the invention reduces manufacturing steps and potential failure points, thereby improving yield while maintaining memory capacity.
4Ease of operation
If conventional nonvolatile memory arrays use traditional erase methods, then erasing of selected memory cells is achieved, but data disturbance occurs in unselected cells
Solution Approach 1:
The patent applies local quality by using different conductivity types for different portions of the gate electrode. The first portion has first conductivity type and the second portion has second conductivity type, allowing selective control of erase operations. This enables precise local erasing of selected memory cells while maintaining data integrity in unselected cells through localized electrical field control.
Solution Approach 2:
The patent inverts the traditional approach by using opposite conductivity types in adjacent portions of the gate electrode. This inversion allows for differential control where one portion can be used for programming while the other is used for erasing, enabling selective operations that prevent disturb to unselected cells by creating opposing electrical field configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of nonvolatile memory arrays by reducing erase disturb and improving data integrity, as charge carriers tunnel through distinct dielectric layers, thereby prolonging dielectric breakdown and minimizing data disturbance during erasing operations.
Implementation Method 1
uses programming and erasing methods allowing charge carriers to tunnel through different dielectric layers within memory cells
Data Source
AI summary
An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. In an embodiment, the capacitor and tunnel structure can include upper electrodes, wherein the upper electrode of the capacitor has a first conductivity type, and the upper electrode of the tunnel structure includes at least a portion that has a second conductivity type opposite the first conductivity type. In another embodiment, a process of forming the nonvolatile memory is performed using a single poly process. In a further embodiment, charge carriers can tunnel through a gate dielectric layer of the state transistor during programming and tunnel through a tunnel dielectric of the tunnel transistor during erasing.