Nonvolatile Memory Cell Single-Layer Gate Integration

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Solution Overview

Problem

The integration of nonvolatile memory devices into system-on-chip (SOC) products poses a challenge due to the mismatch in process technologies between single-gate logic devices and stack-gate nonvolatile memory devices, requiring a more complex fabrication process.

Innovation Solution

The development of a nonvolatile memory cell with a MOS capacitor structure and half-MOS transistors, where the charge storage element is coupled between two half-MOS transistors, allowing for a single-layered gate structure that is compatible with CMOS circuits, facilitating simpler fabrication and integration with logic devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If stack gate structure is used for nonvolatile memory devices, then data retention capability is improved, but process technology compatibility with logic devices deteriorates

Engineering Contradiction:

Improvedata retention capabilityVSAvoidprocess technology compatibility

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The memory cell is divided into two separate transistors: a charge storage transistor with stack gate structure (floating gate, inter-gate dielectric, control gate) for data retention, and a selection transistor with single gate structure for process compatibility. This segmentation allows each transistor to be optimized for its specific function while maintaining overall process compatibility with CMOS logic devices.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The selection transistor serves multiple functions: it selects the memory cell for read/write operations and simultaneously provides a simplified single-gate structure that is compatible with standard CMOS fabrication processes. This multi-functionality resolves the contradiction by making the selection device universal for both cell selection and process compatibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of manufacture

If single-layered gate structure is used for nonvolatile memory devices, then process technology compatibility with logic devices is improved, but device performance deteriorates

Engineering Contradiction:

Improveprocess technology compatibilityVSAvoiddevice performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The memory cell is segmented into two transistors with different gate structures: the charge storage transistor uses a single-layered gate structure for ease of manufacture and process compatibility, while the selection transistor also uses a single-layered gate structure. This segmentation maintains manufacturing simplicity while achieving functional requirements through the specific configuration of the charge storage element.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The floating gate acts as an intermediary between the control gate and the channel, enabling charge storage functionality without requiring a complex multi-layer gate structure. This intermediary mechanism allows the charge storage transistor to achieve nonvolatile memory functionality while maintaining a simpler single-layered gate structure that is compatible with standard CMOS processes.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If stack gate structure is used, then charge storage capability is improved, but fabrication complexity increases

Engineering Contradiction:

Improvecharge storage capabilityVSAvoidfabrication complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory cell is segmented into two transistors where the charge storage transistor is specifically designed with a floating gate structure optimized for charge storage capability, while the selection transistor uses a simpler single-gate structure. This segmentation concentrates the charge storage functionality in one transistor, reducing overall fabrication complexity compared to using stack gate structures throughout.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The floating gate, inter-gate dielectric, and control gate of the charge storage transistor are merged into a integrated structure that provides efficient charge storage. This merging of components into a unified charge storage element achieves high charge storage capability while managing fabrication complexity through a standardized integrated approach.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9741729B2Nonvolatile memory cells, nonvolatile memory cell arrays including the same, and methods of fabricating the same

Publication Date: 2017.08.22 SK HYNIX INC

AI summary

Nonvolatile memory devices includes a charge storage element having a MOS capacitor structure and including a control gate terminal connected to a word line and a body terminal connected to a body bias line, a first half-MOS transistor having a first selection gate terminal connected to the word line and a first impurity junction terminal connected to a bit line and sharing the body terminal with the charge storage element, and a second half-MOS transistor having a second selection gate terminal connected to the word line and a second impurity junction terminal connected to a source line and sharing the body terminal with the charge storage element. The charge storage element is coupled between the first and second half-MOS transistors so that the first half-MOS transistor, the charge storage element, and the second half-MOS transistor are connected in series.