Nonvolatile Memory Cell Gate Oxide Uniformity
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Solution Overview
Problem
Conventional vertical-type nonvolatile memory cells face issues with residual silicon nitride at corners during dry etching and thinner gate oxide layers, affecting electrical characteristics and stability.
Innovation Solution
A method involving a semiconductor substrate with a conducting layer and spacer layer, forming trenches, and using an oxide-nitride-oxide dielectric layer to create polysilicon floating gates and control gates, while avoiding residual silicon nitride through controlled etching and polishing steps to maintain uniformity and integrity of the gate oxide layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dry etching is performed on ONO dielectric layer to leave a portion on the side surfaces of the trench, then the manufacturing process can be simplified, but residual silicon nitride is produced at corners and the gate oxide layer becomes non-uniform
Solution Approach 1:
The patent segments the dielectric layer into two distinct parts: the ONO dielectric layer deposited on the spacer layer, and the gate oxide layer deposited at the bottom of the trench. This segmentation allows selective removal of the ONO layer while preserving the gate oxide layer, preventing residual silicon nitride contamination and maintaining gate oxide uniformity.
Solution Approach 2:
The patent performs preliminary deposition of the gate oxide layer at the bottom of the trench before depositing the ONO dielectric layer on the spacer layer. This preliminary action ensures that the gate oxide layer is already in place and protected, preventing subsequent contamination from residual silicon nitride during the etching process.
2Productivity
If the ONO dielectric layer is deposited on the spacer layer and anisotropic etching is performed, then the process can be completed in fewer steps, but residual silicon nitride remains at corners affecting device stability
Solution Approach 1:
The patent extracts the problematic silicon nitride spacer layer material from the final memory cell structure by selectively removing it after the gate oxide layer has been deposited. This extraction eliminates the source of residual contamination while maintaining manufacturing efficiency through the sequential deposition and selective removal process.
Solution Approach 2:
The patent introduces the gate oxide layer as an intermediary protective layer deposited at the trench bottom before ONO dielectric layer deposition. This intermediary layer acts as a barrier that prevents residual silicon nitride from contaminating the critical gate oxide region, thereby maintaining device stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical characteristics and stability of the nonvolatile memory cells by preventing residual silicon nitride formation and ensuring a uniform gate oxide layer, thereby improving memory cell performance and reducing manufacturing costs.
Implementation Method 1
An oxide-nitride-oxide (ONO) dielectric layer 16 is disposed between the control gate 17 and each of the floating gates 11
Implementation Method 2
Anisotropic etching is performed for leaving a portion 16 of the ONO dielectric layer on the plural side surfaces of the trench
Implementation Method 3
A portion of the second polysilicon layer on the spacer layer is removed (e.g. by chemically mechanical polishing (CMP) of the planarization polishing technology)
Data Source
AI summary
A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.