Non-volatile Memory Cell With Self-Aligned Floating And Erase Gates
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Solution Overview
Problem
The manufacturing of semiconductor floating gate memory cell arrays faces challenges in precise alignment of components, leading to issues such as low source junction breakdown and limited program-disturb window, as the dimensions of the cells shrink, and the control gate's dual voltage operation complicates insulation and capacitive coupling.
Innovation Solution
The method involves forming an electrically isolated coupling gate inside the trench for capacitive coupling to the floating gates, allowing the source region to operate at a lower voltage and using a thicker isolation layer between the coupling gate and source, while the floating gate and source have thinner insulation, enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the control gate is used for both low voltage operation and high voltage erase operation, then the memory cell can perform both functions with a single gate, but it becomes difficult to provide sufficient insulation for high voltage operation while maintaining electrical connectivity for low voltage operation
Solution Approach 1:
The gate structure is segmented into two separate gates: a control gate for low voltage operation and an erase gate for high voltage operation. This segmentation allows each gate to be optimized for its specific voltage requirement, with the erase gate providing sufficient insulation for high voltage while the control gate maintains electrical connectivity for low voltage operation.
Solution Approach 2:
The erase function is extracted from the control gate and assigned to a separate erase gate. This extraction resolves the conflict by removing the high voltage erase operation from the control gate, allowing the control gate to focus solely on low voltage operation without insulation conflicts.
2Reliability
If the control gate is positioned close to the floating gate for erase operation, then erase efficiency is improved, but unwanted capacitive coupling between the control gate and floating gate increases
Solution Approach 1:
The erase function is extracted to a separate erase gate positioned adjacent to the floating gate, while the control gate is positioned over the channel region. This spatial extraction allows the erase gate to provide strong capacitive coupling for efficient erase operation without the control gate interfering or creating unwanted coupling.
Solution Approach 2:
The gate functions are segmented spatially: the erase gate is positioned adjacent to the floating gate for direct capacitive coupling during erase, while the control gate is positioned over the channel region for control during read and program operations, minimizing unwanted coupling.
3Productivity
If memory cell dimensions are reduced to increase cell density, then the number of memory cells per wafer increases, but alignment precision of source, drain, control gate, and floating gate becomes more difficult to maintain
Solution Approach 1:
The control gate and erase gate are formed in the same lithographic step as a single continuous polysilicon layer, ensuring perfect alignment between the two gates and the underlying channel region. This merging of formation steps eliminates alignment errors that would occur if the gates were formed separately.
Solution Approach 2:
The control gate and erase gate are formed preliminarily as a single structure before any alignment-critical features are added. This preliminary formation establishes a reference framework that simplifies subsequent alignment steps and maintains precision even as dimensions are reduced.
4Ease of manufacture
If a single polysilicon layer is used for both control gate and erase gate, then the manufacturing process is simplified, but the gates cannot be independently optimized for different voltage requirements
Solution Approach 1:
While using a single polysilicon layer for formation, the structure is segmented into two distinct gate regions (control gate over channel, erase gate adjacent to floating gate) that can be independently connected to different voltage sources. This segmentation maintains manufacturing simplicity while enabling independent voltage control.
Solution Approach 2:
The single polysilicon layer serves multiple functions: forming both the control gate and erase gate structures, providing electrical connectivity to both gates, and maintaining structural integrity. This universal material choice simplifies manufacturing while the geometric configuration enables independent voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for improved programming voltage without source voltage breakdown, reduces capacitive coupling, and enhances the program, read, and erase efficiencies of the memory cells, enabling smaller cell sizes with increased reliability.
Implementation Method 1
the floating gate includes an edge that directly faces and is insulated from the notch. During an erase operation, the notch of the erase gate enhances Fowler-Nordheim tunneling from the floating gate
Implementation Method 2
forming an electrically isolated coupling gate inside the trench for capacitive coupling to the floating gates
Data Source
Figure 1A~1F
Figure 2A~2B
Figure 2C
AI summary
A memory device, and method of making the same, in which a trench is formed into a substrate of semiconductor material. The source region is formed under the trench, and the channel region between the source and drain regions includes a first portion that extends substantially along a sidewall of the trench and a second portion that extends substantially along the surface of the substrate. The floating gate is disposed in the trench, and is insulated from the channel region first portion for controlling its conductivity. A control gate is disposed over and insulated from the channel region second portion, for controlling its conductivity. An erase gate is disposed at least partially over and insulated from the floating gate. An electrically conductive coupling gate is disposed in the trench, adjacent to and insulated from the floating gate, and over and insulated from the source region.