Non-volatile Memory Cell with Lateral Charge Trapping Layers
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Solution Overview
Problem
Current non-volatile memory technologies face challenges in integrating multiple bits in a single memory cell due to complex fabrication processes and interference between data bits, leading to increased costs and reduced reliability.
Innovation Solution
A non-volatile memory design featuring a memory cell with multiple charge trapping layers on both sides of gates, using materials like nanocrystal, tantalum oxide, or silicon nitride, and a semiconductor layer with a doped region as a common source/drain, allowing for self-aligned charge trapping layer formation and independent programming, erasing, and reading of bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple polysilicon layers and silicon oxide layers are formed in EEPROM to achieve multi-bit storage, then storage capacity is improved, but fabrication process complexity and cost increase
Solution Approach 1:
The patent transitions from vertical stacking of multiple gates (3D complexity) to lateral arrangement of charge trapping layers on opposite sides of a single gate (2D spatial utilization). This allows multi-bit storage by positioning first and second charge trapping layers on opposite sides of the gate, enabling independent bit storage without increasing vertical layer count or fabrication complexity.
Solution Approach 2:
The charge trapping layer is segmented into distinct first and second charge trapping layers positioned on opposite sides of the gate. Each segment functions as an independent storage region for separate bits, allowing multi-bit storage within a single memory cell while maintaining a unified gate structure and simplifying fabrication processes.
2Quantity of substance
If multiple charge trapping layers are placed adjacent to each other for multi-bit storage, then storage density is improved, but interference between data bits occurs reducing reliability
Solution Approach 1:
The patent employs asymmetric positioning of charge trapping layers relative to the gate, placing first and second charge trapping layers on opposite sides of the gate structure. This asymmetric arrangement creates spatial separation that prevents electric field interference between adjacent charge trapping layers, ensuring independent control and reading of stored bits while maintaining high storage density.
Solution Approach 2:
The gate structure serves as an intermediary element that physically separates and electrically isolates the first and second charge trapping layers. By positioning charge trapping layers on opposite sides of the gate, the gate acts as a barrier that prevents charge leakage and interference between adjacent storage regions, thereby maintaining data integrity and reliability.
3Quantity of substance
If double-gate design is used for memory cell, then storage capacity is improved, but device area increases reducing integration
Solution Approach 1:
The patent utilizes lateral spatial arrangement of charge trapping layers on opposite sides of a single gate, effectively using the horizontal plane for multi-bit storage. This approach achieves multi-bit capacity without requiring additional vertical gate structures, thereby maintaining compact device footprint and high integration density while storing multiple bits in a single memory cell.
Solution Approach 2:
A single gate structure performs multiple functions by controlling both first and second charge trapping layers positioned on its opposite sides. This universal gate design enables multi-bit storage capability within a single memory cell without requiring separate gate structures for each bit, thereby reducing device area and improving integration compared to traditional double-gate designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high integration density and improved reliability by allowing multi-bit storage in a single memory cell without interference between bits, enhancing electrical performance and reducing fabrication complexity.
Implementation Method 1
a first charge trapping layer and a second charge trapping layer respectively disposed at both sides of the first gate... a third charge trapping layer and a fourth charge trapping layer respectively disposed at both sides of the second gate
Data Source
AI summary
The memory cell includes a first unit, a semiconductor layer, a second unit, and a doped region. The first unit includes a first gate, a first charge trapping layer, and a second charge trapping layer. The first and the second charge trapping layer are respectively disposed on both sides of the first gate. The semiconductor layer is disposed on the first unit. The second unit is disposed on the semiconductor layer and is in mirror symmetry to the first unit. The second unit includes a second gate and a third and a fourth charge trapping layer respectively disposed on both sides of the second gate. The doped region is disposed at both sides of the semiconductor layer and serves as a common source/drain region of both the first and the second unit.