Nonvolatile Memory Cell Segmentation for High Density Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face limitations in efficiently storing and retrieving multiple bits of data in a single memory cell, particularly in achieving high data storage capacity and reliability with faster write/read operations.
Innovation Solution
A nonvolatile memory apparatus and method that utilizes a plurality of memory cells, an encoder to encode data into write data, and control logic to manage the states of these cells, allowing for the storage of 2 bits of first data and 2 bits of second data in 3 memory cells, with specific control operations to change or maintain cell states based on encoded data, enabling efficient storage and retrieval of 4 bits of information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits of data are stored in a single memory cell using multi-level cells, then storage capacity is improved, but write and read operation speeds deteriorate and reliability decreases
Solution Approach 1:
The patent divides the storage function into multiple single-level memory cells (first, second, and third cells) that work together to store multiple bits of data. Instead of using a single multi-level cell, the system segments the data storage across multiple simpler cells, where each cell stores a portion of the data (e.g., first data in the first cell, second data in the second cell, third data in the third cell), thereby maintaining fast write/read speeds while achieving high storage capacity.
Solution Approach 2:
The patent implements a hierarchical storage structure where multiple single-level memory cells are nested within a logical multi-bit storage unit. The first, second, and third memory cells are organized to collectively function as a multi-bit storage element, with control logic that manages their coordinated operation. This nested arrangement allows the system to achieve multi-bit storage capacity without sacrificing the speed advantages of single-level cells.
2Quantity of substance
If multiple bits of data are stored in a single memory cell using multi-level cells, then storage capacity is improved, but data reliability deteriorates
Solution Approach 1:
The patent segments the storage of multiple bits of data across multiple single-level memory cells rather than concentrating all bits in a single multi-level cell. Each single-level cell maintains its own distinct state with higher stability, and the control logic coordinates their combined state to represent the full multi-bit data. This segmentation preserves data reliability by avoiding the inherent instability of multi-level cell states while achieving high storage capacity.
3Productivity
If single-level memory cells are used for storage, then write and read operation speeds are improved, but storage capacity deteriorates
Solution Approach 1:
The patent merges multiple single-level memory cells (first, second, and third cells) to function collectively as a multi-bit storage unit. By combining the storage capacity of several single-level cells, the system achieves the equivalent functionality of a multi-level cell while preserving the speed advantages of single-level technology. The control logic manages this merged structure to enable efficient write and read operations across all cells simultaneously or in coordinated sequences.
4Quantity of substance
If more memory cells are used to store multiple bits, then storage capacity and reliability are improved, but device complexity increases
Solution Approach 1:
The control logic in the patent is designed with multi-functionality to manage multiple single-level memory cells efficiently. A single control logic unit performs multiple functions: it controls the write operation to first, second, and third cells; manages the read operation from all three cells; and coordinates the combination of data from individual cells to form complete multi-bit data. This universal control approach reduces overall system complexity by consolidating control functions rather than requiring separate control circuits for each cell or operation.
Data Source
AI summary
A method operates a nonvolatile memory apparatus. The method includes performing a first write operation to store first data in first to third memory cells; and performing a second write operation to store second data in the first to third memory cells in which the first data has been stored, wherein, as a result of the first write operation and the second write operation, each of the first to third memory cells has one of first to third states.