Nonvolatile Memory Cell With Sidewall Control Gate
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in achieving high density and operational reliability while maintaining a small cell size and low driving voltage, with the split gate structure being unsuitable for high density due to its large cell size and the stack gate structure experiencing issues with over erase and operational complexity.
Innovation Solution
A nonvolatile memory cell design featuring a floating gate with a halo region and a control gate overlapping at least one sidewall, along with a lightly doped drain region, to enhance hot carrier generation and improve program efficiency, while maintaining stable threshold voltage and reducing cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a split gate structure is used to improve operational reliability, then the threshold voltage can be maintained constantly and over erase can be prevented, but the cell size becomes great and high density integration becomes difficult
Solution Approach 1:
The gate structure is segmented into a control gate and a floating gate that are spatially separated. The control gate is positioned above the substrate while the floating gate is positioned laterally adjacent to it, creating a split gate configuration. This segmentation allows the device to achieve split gate functionality without requiring the large overlapping area of traditional split gate structures, thus reducing cell size while maintaining operational reliability.
Solution Approach 2:
The invention transitions from a planar split gate structure to a three-dimensional configuration where the control gate and floating gate are positioned at different vertical levels. The control gate is formed above the substrate surface while the floating gate is positioned laterally and vertically adjacent to it. This dimensional change allows for compact cell layout while maintaining the electrical characteristics of a split gate structure.
2Area of stationary object
If a stack gate structure is used to reduce cell size for high density, then the construction is simple and fabrication is easy, but operational reliability deteriorates due to over erase and operational complexity increases
Solution Approach 1:
The gate structure is segmented into a control gate and a floating gate that are spatially separated. The control gate is positioned above the substrate while the floating gate is positioned laterally adjacent to it, creating a split gate configuration. This segmentation allows the device to achieve split gate functionality without requiring the large overlapping area of traditional split gate structures, thus reducing cell size while maintaining operational reliability.
3Reliability
If a traditional split gate structure is used to maintain constant threshold voltage, then operational reliability improves, but the cell size becomes great and additional area is required
Solution Approach 1:
The invention transitions from a planar split gate structure to a three-dimensional configuration where the control gate and floating gate are positioned at different vertical levels. The control gate is formed above the substrate surface while the floating gate is positioned laterally and vertically adjacent to it. This dimensional change allows for compact cell layout while maintaining the electrical characteristics of a split gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the integration density, reduces driving voltage, and enhances operational reliability by increasing the coupling ratio and generating additional hot carriers, thereby improving program and erase operations.
Implementation Method 1
enhance hot carrier generation and improve program efficiency
Data Source
AI summary
A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.