Non-volatile Memory Device With Charge Blocking Layer
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to improve the operation characteristics and integration degree of embedded memory in System on Chip (SoC) technology without requiring additional processes beyond the logic process, as existing methods often deteriorate device characteristics.
Innovation Solution
A non-volatile memory device is designed with a floating gate, selection gate, and control plug, which are formed through a predetermined logic process, along with a charge blocking layer to enhance coupling and integration, allowing for improved operation characteristics without the need for additional processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If additional processes are performed beyond the predetermined logic process to improve embedded memory characteristics, then operation characteristics and integration degree are improved, but device characteristics deteriorate
Solution Approach 1:
The patent combines the formation of the control gate and selection gate into a single simultaneous deposition process, eliminating the need for separate additional processes. The control gate and selection gate are formed as integrated structures that work together to improve embedded memory characteristics without requiring extra fabrication steps that would harm device reliability.
Solution Approach 2:
The control gate structure serves multiple functions: it acts as both a control gate for the memory transistor and a selection gate for channel selection. This multi-functional design allows the embedded memory to achieve improved operation characteristics through a single structure formed during the logic process, avoiding additional specialized processes.
2Manufacturing precision
If additional processes are performed beyond the predetermined logic process to improve embedded memory characteristics, then integration degree is improved, but process complexity increases
Solution Approach 1:
The patent merges the control gate and selection gate formation into a single process step where both gates are deposited simultaneously. This integration reduces process complexity by eliminating sequential steps while achieving high integration degree through the combined multi-functional gate structure.
Solution Approach 2:
By designing the control gate to simultaneously function as both control and selection gates, the patent achieves high integration degree without adding process complexity. The single structure performs multiple functions that would otherwise require separate dedicated structures and processes.
3Ease of manufacture
If conventional logic process is used without additional processes, then process simplicity is maintained, but operation characteristics and integration degree of embedded memory are insufficient
Solution Approach 1:
The control gate is designed to serve dual functions as both control gate and selection gate, enabling the embedded memory to achieve improved operation characteristics and integration degree within the conventional logic process framework without requiring additional manufacturing steps.
Solution Approach 2:
The patent modifies the control gate structure parameters (forming it with specific dimensions and positioning it at defined locations relative to floating gates) to enable it to perform multiple functions. These parameter adjustments allow the single gate structure to provide both control and selection functionality, improving embedded memory performance within existing process constraints.
Data Source
AI summary
A non-volatile memory device includes an isolation layer formed over a substrate to define an active region, a floating gate formed over the substrate, a selection gate formed over the substrate on one side of the floating gate and formed to be adjacent to the floating gate with a first gap from the floating gate, a control plug formed over the isolation layer on the other side of the floating gate and formed to be adjacent to the floating gate with a second gap from the floating gate, and a charge blocking layer formed to gap-fill the first gap and the second gap.