Non-Volatile Memory Array for Accurate Compute-in-Memory
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Solution Overview
Problem
Existing compute-in-memory (CIM) operations face accuracy limitations due to data converter resolution constraints and signal degradation during analog accumulation, particularly in CIM memory devices, which are vulnerable to noise signals and have a restricted sampling range.
Innovation Solution
The CIM memory device digitalizes the CIM result by generating individual output voltages from memory cells using non-volatile memory with high and low resistances, coupled with bias circuits and an adder tree circuit to ensure accurate CIM operations without signal margin loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If analog accumulation is used in CIM memory device, then computation can be performed in memory, but signal degradation and noise vulnerability occur reducing accuracy
Solution Approach 1:
The patent segments the computation process into multiple discrete steps: individual memory cell evaluation generates intermediate results, which are then accumulated in a separate adder tree circuit. This separation isolates the sensitive accumulation process from the memory array, reducing noise coupling and signal degradation while maintaining computational efficiency.
Solution Approach 2:
The patent introduces intermediate voltage nodes and buffer circuits between the memory cells and the final output. These intermediaries isolate the memory cells from direct loading effects during readout, preventing signal degradation and allowing accurate analog-to-digital conversion without losing computation precision.
2Device complexity
If data converter resolution is limited, then device complexity is reduced, but CIM operation accuracy deteriorates
Solution Approach 1:
The patent performs preliminary computation operations directly within the memory cells before data leaves the memory array. Each memory cell pre-evaluates its contribution to the final result and outputs an intermediate voltage representing this partial computation. This preliminary action reduces the burden on subsequent data converters, allowing accurate results with lower resolution converters.
Solution Approach 2:
The patent replaces complex high-resolution digital-to-analog and analog-to-digital conversion systems with simpler voltage division and resistance-based computation circuits. By using the inherent electrical properties of memory cells (resistance ratios) to directly generate computation results, the system achieves high accuracy without requiring complex data converters.
3Device complexity
If sampling range is restricted in analog accumulation, then device complexity is reduced, but accuracy of CIM operation is limited
Solution Approach 1:
The patent transitions from purely analog accumulation to a hybrid approach where memory cells operate in the resistance domain, generate voltages that are then accumulated in the voltage domain using simple adder circuits. This dimensional change allows the system to maintain a wide effective sampling range through the resistance ratios of memory cells while using simple analog adders for accumulation, achieving high precision without complex wide-range analog circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances CIM accuracy by providing distinct output voltages for different bit values, overcoming the limitations of analog accumulation and maintaining precision in CIM operations.
Implementation Method 1
a memory unit configured to store a bit of the weight data in a first state or a second state
Implementation Method 2
a second terminal of the fourth transistor is coupled to a second node, and an output terminal of the memory cell is configured to generate different voltages at the second node according to the memory state
Data Source
AI summary
A memory device is provided, including a non-volatile memory array including multiple memory cells, in which the memory cells arranged in a same row are configured to store corresponding weight data and are coupled to a same word line in multiple word lines; a word line driver configured to transmit multiple word line signals according to multiple input data signals to the word lines to perform a compute-in-memory (CIM) operation of the input data signals and the weight data stored in the non-volatile memory array; and an adder tree circuit coupled to the memory cells. Each of the memory cells in the same row is configured to generate a corresponding output voltage of the CIM operation to the adder tree circuit.