Non-Volatile Memory Circuit for Power Loss Data Backup
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Solution Overview
Problem
Existing systems require large backup power sources to prevent data loss during power interruptions, which occupy critical space and consume excessive power, especially in complex and data-intensive vehicular electronic steering systems.
Innovation Solution
A circuit utilizing a matrix of non-volatile memory cells with a single detached EEPROM block that can write data independently, reducing the need for additional power and space by allowing concurrent programming with a single pulse and eliminating the requirement for 1/3 and 2/3 voltages, thereby optimizing power consumption and area complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large backup power sources (capacitors or batteries) are used to prevent data loss during power interruptions, then data integrity is improved, but device area and power consumption increase significantly
Solution Approach 1:
The patent segments the memory system into two distinct parts: a main volatile memory array and a separate small non-volatile memory block. This segmentation allows the system to use minimal non-volatile memory (only enough to store backup data) rather than requiring large backup power sources, thereby reducing device area while maintaining data integrity through selective data preservation in the non-volatile block.
Solution Approach 2:
The patent extracts the backup power requirement by implementing a non-volatile memory block that inherently retains data without power. This eliminates the need for large capacitors or batteries, as the non-volatile memory naturally preserves critical data during power interruptions, thus solving the contradiction between data integrity and device area.
2Reliability
If large backup power sources are used to maintain circuit operation during shutdown, then data saving capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the memory system into volatile and non-volatile portions, allowing critical data to be stored in the non-volatile block which consumes no power for data retention. This eliminates the need for continuous power supply to large backup sources, thereby reducing power consumption while maintaining data saving capability.
Solution Approach 2:
The patent extracts the power consumption issue by using non-volatile memory technology that inherently retains data without requiring power. This eliminates the need for large capacitors or batteries that would continuously consume power, thus solving the contradiction between data saving capability and power consumption.
3Reliability
If traditional EEPROM matrix programming is used during power loss, then data backup is achieved, but programming time and complexity increase due to multiple voltage requirements
Solution Approach 1:
The patent segments the memory architecture so that the non-volatile block operates independently from the main EEPROM matrix. This independent structure allows simplified programming operations on the non-volatile block during power loss events, reducing programming complexity and time compared to traditional matrix-based EEPROM programming that requires multiple voltage levels and coordinated row/column operations.
Solution Approach 2:
The patent extracts the complexity of traditional EEPROM programming by implementing a dedicated non-volatile memory block with simplified write operations. This block can be programmed with a single control pulse without requiring the complex multi-voltage coordination needed for traditional EEPROM matrix programming, thus reducing programming complexity while maintaining data backup reliability.
Data Source
AI summary
A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).