Nonvolatile Memory Clock Signal Generation for Temperature Compensation
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Solution Overview
Problem
Nonvolatile memory devices experience errors and reliability issues due to varying operating characteristics with temperature, leading to potential data loss and increased operating time.
Innovation Solution
A nonvolatile memory device design incorporating a memory cell array with multiple planes, a first clock generator producing a fixed clock signal, and a second clock generator producing a temperature-varying clock signal, along with clock switching controllers and page buffers that adjust operations based on these signals to minimize temperature-related errors and optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single fixed clock signal is used for memory operations, then device complexity is reduced, but reliability deteriorates due to temperature variations causing operating characteristic changes and errors
Solution Approach 1:
The clock signal generation is segmented into multiple independent clock generators (first clock generator for normal temperature, second clock generator for high temperature). Each generator produces clock signals optimized for specific temperature ranges, allowing the system to maintain reliability across varying temperatures without requiring a single complex adaptive clock generator.
Solution Approach 2:
The system dynamically switches between different clock generators based on temperature conditions. The clock switching controller monitors temperature and selects the appropriate clock signal source, enabling the system to adapt its clock signal characteristics to match current operating conditions, thereby maintaining reliability without permanent complexity.
2Reliability
If clock signal period is fixed, then device complexity is reduced, but reliability deteriorates as temperature variations cause operating characteristics to change and errors to occur
Solution Approach 1:
Different clock signal characteristics (fixed period for normal temperature, variable period for high temperature) are applied locally based on operating conditions. The first clock generator provides fixed-period signals suitable for normal operation, while the second clock generator provides variable-period signals optimized for high-temperature compensation, ensuring operation accuracy without uniform complexity throughout the system.
Solution Approach 2:
The clock signal period parameter is changed based on temperature conditions. The second clock generator modifies the clock period in response to high temperature to compensate for operating characteristic changes, while the first clock generator maintains a fixed period for normal conditions. This parameter adaptation improves reliability without requiring continuous complex control.
3Reliability
If temperature compensation is implemented with multiple clock generators, then reliability is improved, but device complexity increases
Solution Approach 1:
Temperature compensation is prepared in advance by having both clock generators ready and configured for their respective temperature ranges. The system pre-establishes the appropriate clock signal characteristics before temperature-induced errors occur, allowing seamless switching based on temperature conditions without requiring complex real-time calculation or adjustment mechanisms.
Solution Approach 2:
The clock switching controller acts as an intermediary that manages the complexity of coordinating multiple clock generators. It monitors temperature conditions and automatically selects the appropriate clock source, isolating the complexity of temperature compensation from the rest of the memory system and simplifying the overall control architecture.
Data Source
AI summary
A nonvolatile memory device includes: a memory cell array including three or more planes; a first clock generator generating a first clock signal having a first period; a second clock generator generating a second clock signal having a second period that varies with the temperature; a plurality of clock switching controllers outputting one of the first and second clock signals as a reference clock signal; a control logic including a plurality of bitline shutoff generators, which output a plurality of bitline shutoff signals based on the reference clock signal; and a plurality of page buffers connecting bitlines of the planes and data latch nodes in accordance with the bitline shutoff signals.