Nonvolatile Memory Device Concurrent Data Programming

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving improved operating speed and efficiency, particularly in programming operations, due to limitations in data handling and verification processes.

Innovation Solution

A nonvolatile memory device with a memory cell array, page buffer circuit, and row decoder, which performs program operations using multiple verification voltages and data loops, allowing for efficient data programming and verification by storing and processing first and second data sets concurrently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If sequential data input and program operation are performed, then data integrity is maintained, but operating speed is reduced due to waiting time for data input

Engineering Contradiction:
Improveoperating speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The controller loads first data into the page buffer circuit before the program operation starts. When the program operation is initiated, the page buffer circuit already contains the first data, eliminating waiting time. The controller then provides second data while the program operation using first data is ongoing, ensuring data is ready in advance without compromising integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system performs data input and program operation concurrently rather than sequentially. The controller continues providing data (first data then second data) while the program operation is executing, making the data input process continuous and overlapping with the program operation to maximize utilization of both operations

Inventive Principle:
Principle #20Continuity of useful action

2Reliability

If multiple verification voltages are used in program loops, then data programming reliability is improved, but program operation time increases

Engineering Contradiction:
Improvedata programming reliabilityVSAvoidprogram operation time
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The controller loads first data into the page buffer circuit before initiating the program operation. This preliminary data loading allows the program operation to start immediately without waiting for data input, reducing the overall time while maintaining the multi-verification-voltage process for reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system performs data input and program operation concurrently. The controller continues providing data (first data then second data) while the program operation is executing, making the data input process continuous and overlapping with the program operation to maximize utilization of both operations

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11227659B2Nonvolatile memory device and storage device including nonvolatile memory device
Publication Date: 2022.01.18 SAMSUNG ELECTRONICS CO LTD
  • US11227659B2 patent drawing
  • US11227659B2 patent drawing
  • US11227659B2 patent drawing

AI summary

A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.