Non-volatile Memory Configuring Low Power DRAM
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Configuring Low Power Dynamic Random Access Memory (LPDRAM) devices for low power operation is challenging due to sensitivity to environmental conditions, requiring complex routines that can lead to data corruption and system failure, especially in extreme temperatures and voltages, and poses issues with future compatibility and parts availability.
Innovation Solution
Pairing LPDRAM with a non-volatile memory device that executes configuration routines stored in the non-volatile memory, allowing self-contained configuration under local control, eliminating the need for system processor involvement and simplifying the design process by moving configuration out of the operating system and processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If LPDRAM configuration is performed through complex routines in the operating system or processor, then low power operation can be achieved, but system reliability decreases and data corruption risks increase
Solution Approach 1:
The patent extracts the LPDRAM configuration routines from the operating system or processor and places them in a separate, dedicated configuration memory device. This isolation prevents the complex configuration routines from interfering with critical system operations, thereby improving reliability while maintaining the ability to achieve low power operation through proper configuration.
Solution Approach 2:
The patent introduces a dedicated configuration memory device as an intermediary between the processor and the LPDRAM. This intermediary holds the configuration routines and parameters, allowing the processor to configure LPDRAM without executing complex routines during normal operation, thus improving both reliability and power efficiency.
2Use of energy by moving object
If LPDRAM configuration routines are compiled into the operating system, then low power operation can be achieved, but device complexity and design testing complexity increase
Solution Approach 1:
The patent extracts configuration routines from the operating system and stores them in a separate configuration memory device. This separation reduces the complexity of the operating system and eliminates the need for extensive testing and integration of configuration routines into the OS, while still enabling low power operation through dedicated configuration.
3Reliability
If conventional DRAM uses higher power usage settings with refresh rates higher than required, then system reliability improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic configuration of LPDRAM refresh rates based on actual operating conditions. The configuration memory device stores multiple refresh rate settings that can be selected based on temperature, workload, and power availability, allowing the system to maintain data integrity while optimizing power consumption for each operating scenario.
Solution Approach 2:
The patent changes the refresh rate parameter of LPDRAM from a fixed high value to a dynamically adjustable value. By storing multiple refresh rate configurations in the configuration memory device and selecting appropriate values based on operating conditions, the system maintains data state reliability while significantly reducing power consumption during low-activity periods.
4Use of energy by moving object
If LPDRAM configuration is highly dependent on environmental conditions, then power savings can be optimized, but configuration complexity and risk of misconfiguration increase
Solution Approach 1:
The patent performs preliminary configuration of LPDRAM by pre-storing multiple environmental condition profiles and corresponding optimal settings in the configuration memory device. When the system operates, the processor simply selects the appropriate pre-configured profile based on current temperature and workload conditions, eliminating the need for complex real-time calculations and reducing the risk of misconfiguration.
Data Source
AI summary
Non-volatile memory having a non-volatile memory array adapted to store a configuration routine for a low power dynamic random access memory (LPDRAM), a memory interface for receiving addresses from an external device for access of data stored in the non-volatile memory array, and an internal controller adapted to communicate with a LPDRAM coupled to the non-volatile memory and configure operational settings of the LPDRAM using the configuration routine, as well as systems containing similar non-volatile memory.