Nonvolatile Memory Control Gate MOL Metal Formation

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Solution Overview

Problem

Existing nonvolatile memory cell manufacturing techniques face challenges such as high costs and defect rates due to chemical mechanical polishing of polysilicon, and sensitivity issues at small technology nodes like 28 nm, which also affect high-k metal gate integration and encapsulation of logic transistor gates.

Innovation Solution

The method involves forming control gates in the middle-of-line (MOL) process instead of the front-end-of-line (FEOL), using a separate photolithography and self-aligned interlayer dielectric etch to create openings for control gates and contacts, and filling these with metal, thereby avoiding polysilicon deposition and chemical mechanical polishing, and using high-k metal gate integration for select and erase gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chemical mechanical polishing of polysilicon is used in FEOL process, then control gate can be formed, but manufacturing cost increases and defect rate increases

Engineering Contradiction:

Improvecontrol gate formation precisionVSAvoidmanufacturing cost

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent divides the control gate formation process into separate steps: first forming the interlayer dielectric layer, then creating openings, and finally depositing metal material. This segmentation eliminates the need for polysilicon deposition and chemical mechanical polishing, thereby reducing manufacturing complexity and cost while maintaining precision.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the mechanical chemical mechanical polishing process with a metal deposition process. Instead of mechanically removing polysilicon material, the invention uses physical vapor deposition or chemical vapor deposition to deposit metal material into openings, eliminating the harmful mechanical polishing step that causes defects and increases cost.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If chemical mechanical polishing of polysilicon is used, then control gate can be formed, but defect rate increases

Engineering Contradiction:

Improvecontrol gate formation precisionVSAvoiddefect rate

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent extracts and removes the problematic polysilicon material and chemical mechanical polishing step from the manufacturing process. By eliminating the polysilicon deposition and polishing steps entirely, the invention removes the source of defects while maintaining the necessary control gate formation functionality through alternative metal-based approaches.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If FEOL process is used for control gate formation, then nonvolatile memory cell can be manufactured, but high-k metal gate integration is affected and encapsulation of logic transistor gates is compromised

Engineering Contradiction:

Improvenonvolatile memory cell manufacturing efficiencyVSAvoidhigh-k metal gate integration compatibility

Core Design Contradiction:

ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent segments the manufacturing process into distinct front-end and middle-end stages. The control gate formation is moved to the middle-of-line process, allowing the front-end process to complete high-k metal gate integration for logic transistors first, then subsequently forming control gates without interfering with the delicate high-k gate structures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary high-k metal gate integration and logic transistor gate encapsulation before forming the control gates. By completing the sensitive high-k gate structures first, the invention ensures their integrity is maintained, and then proceeds with control gate formation using methods that do not compromise the previously formed structures.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9548312B1Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell

Publication Date: 2017.01.17 GLOBALFOUNDRIES US INC

AI summary

A method includes providing a semiconductor structure including a nonvolatile memory cell element and one or more electrically insulating layers covering the nonvolatile memory cell element. The nonvolatile memory cell element includes a source region, a channel region, a drain region and a floating gate over at least a first portion of the channel region. A first opening is formed in the electrically insulating layers over the floating gate, a control gate insulation layer is deposited, and a second opening is formed in the electrically insulating layers over the drain region. The first opening and the second opening are filled with an electrically conductive material. The electrically conductive material in the first opening provides a control gate of the nonvolatile memory cell element and the electrically conductive material in the second opening provides an electrical contact to the drain region.