Non-volatile Memory Cell-Over-Periphery Vertical Stacking
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Solution Overview
Problem
Contemporary memory devices face challenges in achieving high data storage capacity while maintaining a reduced footprint and uncomplicated wiring designs, necessitating innovative layouts and integration strategies to support multiple functions in electronic devices.
Innovation Solution
The development of a cell-over-periphery (COP) structured non-volatile memory device, where memory groups are vertically stacked on a semiconductor layer with driving circuits and word/bit lines arranged to minimize lateral area, allowing for efficient use of space and simplified wiring configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If memory cell integration is increased to reduce footprint, then area is reduced, but layout and wiring complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory layouts to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked above each other, with word lines and bit lines extending in different horizontal directions (first and second horizontal directions) to access different layers, thereby reducing footprint area while maintaining manageable wiring complexity through vertical stacking rather than lateral expansion
Solution Approach 2:
The memory device is divided into multiple memory groups (first, second, third, fourth memory groups) arranged in a systematic pattern. Each memory group contains memory cells accessible through specific word lines and bit lines, allowing the complex integrated structure to be organized into manageable segments with regular wiring patterns, thus reducing overall layout and wiring complexity despite high integration density
2Quantity of substance
If multiple memory groups are integrated in a compact arrangement, then integration density increases, but wiring configuration complexity increases
Solution Approach 1:
Different memory groups are configured with alternating wire orientations: first and third memory groups have word lines extending in a first horizontal direction and bit lines in a second horizontal direction, while second and fourth memory groups have word lines in the second horizontal direction and bit lines in the first horizontal direction. This asymmetric alternating pattern enables compact integration of multiple memory groups while systematic wiring routing reduces overall wiring configuration complexity
Solution Approach 2:
The driving circuits are designed to universally control multiple memory groups through shared word lines and bit lines. A single driving circuit can control memory cells across different memory groups by selecting appropriate word lines and bit lines, thereby achieving high integration density without proportionally increasing wiring configuration complexity through resource sharing
Data Source
AI summary
A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.