Nonvolatile Memory Device Current Limiting Resistance Layer

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Solution Overview

Problem

In resistive random access memory (ReRAM) devices, the sudden drop in resistance during forming or set processes can lead to excessive current flow, potentially breaking the variable resistance element and damaging driving and protection circuit elements, due to uncontrolled current fluctuations and parasitic capacitances when external resistors are used.

Innovation Solution

Incorporating current limiting resistance layers with resistances of 1 kilo-ohm to 1 mega-ohm in series with the variable resistance element to control and limit electric current, thereby stabilizing filament formation and preventing element breakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage is applied to the variable resistance element during forming or set, then resistance switching occurs, but resistance suddenly falls causing large electric current to flow and break the variable resistance element

Engineering Contradiction:
Improvevariable resistance element durabilityVSAvoidlarge electric current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

A current limiting resistance layer is introduced as an intermediary component between the variable resistance element and the external circuit. This mediator layer limits the electric current flowing through the variable resistance element during forming and set operations, preventing excessive current that would cause element breakage, while still allowing sufficient current for resistance switching.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The current limiting resistance layer is configured beforehand to cushion or absorb excess current before it reaches the variable resistance element. By having this protective layer in place prior to forming or set operations, the system prevents harmful current spikes from damaging the element, addressing the reliability issue proactively.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If the resistance of the variable resistance element is reduced during set processing, then storage capability improves, but large reset current flows during reset and breaks driving circuit elements and protection circuit elements

Engineering Contradiction:
Improvedriving circuit element durabilityVSAvoidlarge reset current
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The current limiting resistance layer serves as a mediator that continuously limits current flow in both directions - during set operations when forming the low resistance state, and during reset operations when the element switches back to high resistance. This prevents large reset currents from damaging driving and protection circuit elements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The resistance value of the current limiting resistance layer is specifically designed to change the overall current characteristics of the memory cell. By selecting appropriate resistance values, the system maintains proper current levels during both set and reset operations, preventing circuit element breakage while preserving storage functionality.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If external resistors are used to limit current, then element breakage is prevented, but uncontrolled current fluctuations and parasitic capacitances cause read threshold deficiencies

Engineering Contradiction:
Improveelement durabilityVSAvoidread threshold accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The current limiting resistance layer is designed with specific resistance parameters (1 kilo-ohm to 1 mega-ohm) that optimize both current limiting and read threshold performance. This parameter selection prevents element breakage while minimizing negative effects on read threshold accuracy, unlike external resistors that cause uncontrolled current fluctuations and parasitic capacitance issues.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The current limiting resistance layer is merged with the variable resistance element to form an integrated memory cell structure. This integration eliminates the parasitic capacitances and connection issues associated with external resistors, while maintaining the current limiting function. The combined structure ensures stable read thresholds and prevents element breakage simultaneously.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively suppresses filament size fluctuations, prevents element breakage, and maintains stable switch characteristics, ensuring consistent set and reset voltages and currents, thus preventing read threshold deficiencies.

Implementation Method 1

a current limiting resistance layer connected in series to the variable resistance element and having resistance of 1 kilo-ohm to 1 mega-ohm

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Implementation Method 2

processing called forming for feeding, while adjusting voltage, electric current and forming a filament (a current path) in nanometer order in the variable resistance element to reduce the resistance

Methodology Applied
Scientific EffectFilament formation:

Implementation Method 3

when voltage is applied to the variable resistance element, resistance suddenly falls at certain voltage. Therefore, it is likely that large electric current flows to the variable resistance element

Methodology Applied
Scientific EffectJoule Heating: Joule Heating

Data Source

PatentUS8410467B2Nonvolatile memory device and method of manufacturing the same
Publication Date: 2013.04.02 KIOXIA CORP
  • US8410467B2 patent drawing
  • US8410467B2 patent drawing
  • US8410467B2 patent drawing

AI summary

According to one embodiment, a nonvolatile memory device includes a first wire, a second wire and a nonvolatile memory cell. The first wire is formed to extend in a first direction, and the second wire is formed at height different from height of the first wire and to extend in a second direction. The nonvolatile memory cell is arranged to be held between the first wire and the second wire in a poison where the first wire and the second wire cross. The nonvolatile memory cell includes a nonvolatile storage layer and a current limiting resistance layer connected in series to the nonvolatile storage layer and having resistance of 1 kilo-ohm to 1 mega-ohm.