Nonvolatile Memory Current Mirror Circuit Design
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Solution Overview
Problem
Conventional nonvolatile memory devices face issues with current and transistor property variations, leading to data readout errors, unstable circuit behavior, and difficulties in design adjustments due to imprecise current ratios and parasitic capacitance differences.
Innovation Solution
The implementation of a nonvolatile memory device with two current detecting circuits, a bias circuit, and a differential amplifying circuit, where transistors are coupled in diode and current mirror configurations to ensure precise current ratios and constant current densities, allowing for accurate data reading and simplified design adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If transistor sizes are adjusted to set current ratios, then current ratio control is achieved, but manufacturing precision deteriorates due to current density variations and property differences
Solution Approach 1:
The patent changes the controlling parameter from transistor size to transistor count. By keeping individual transistor sizes identical and using current mirror circuits, the current ratio is controlled by the number of transistors in parallel rather than by varying transistor dimensions. This resolves the contradiction because identical transistors have consistent properties while the desired current ratio is achieved through configurable transistor counts.
Solution Approach 2:
The patent uses current mirror circuits to copy the current from reference transistors to signal transistors. The current mirror configuration ensures that the current ratio is determined by the ratio of transistor counts rather than by direct size variations. This copying mechanism maintains manufacturing precision while achieving the required current ratio control.
2Adaptability or versatility
If different sized transistors are used to achieve current ratios, then current control flexibility is improved, but reliability deteriorates due to current and property variations
Solution Approach 1:
The patent changes the flexibility parameter from transistor size variation to transistor count configuration. By using identical transistors with consistent properties and controlling current ratios through the number of transistors in parallel, the system maintains reliability while achieving the needed adaptability through configurable transistor counts in different circuit configurations.
Solution Approach 2:
The patent applies homogeneity by using transistors of identical size and properties throughout the circuit. All transistors are manufactured with the same dimensions, ensuring consistent current densities and properties. The desired current ratios are achieved not by heterogeneous transistor sizes but by homogeneous transistor arrays with different counts, thereby maintaining reliability.
3Adaptability or versatility
If transistor sizes are varied for current ratio adjustment, then design adaptability is improved, but device complexity increases due to independent size restrictions and gain limitations
Solution Approach 1:
The patent changes the design parameter from continuous size adjustment to discrete count configuration. By using identical transistors whose effective current ratio is determined by the number of transistors in parallel, the design simplifies the constraints. Instead of managing independent size restrictions and gain limitations for different transistor pairs, the design only needs to configure transistor counts, significantly reducing device complexity while maintaining adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents current and transistor property variations, enhances data reading accuracy, and increases reading speed by stabilizing circuit behavior and optimizing power source wiring.
Implementation Method 1
a first transistor of a first conductive type coupled in a diode configuration. In the first transistor, a current corresponding to the reference cell flows, thereby carrying out current-voltage conversion. The second current detecting circuit has a second transistor of the first conductive type coupled in a diode configuration. In the second transistor, a current corresponding to a memory cell flows, thereby carrying out current-voltage conversion.
Implementation Method 2
The bias circuit has a third transistor of the first conductive type coupled to the first transistor by a current mirror configuration. In the third transistor, a current corresponding to a voltage output from the first transistor flows. The differential amplifier circuit has a fourth transistor of the first conductive type coupled to the second transistor by a current mirror configuration. In the fourth transistor, a current corresponding to a voltage output from the second transistor flows.
Data Source
AI summary
A nonvolatile memory device capable of: preventing variations in current and transistor properties to prevent data readout errors; facilitating design changes with a simplified adjustment of the current ratio of transistors; and achieving increased data reading speed. The memory device comprising: a first current detecting circuit comprising a first transistor of a first conductive type coupled in a diode configuration, wherein current flows according to a reference cell through the first transistor; a second current detecting circuit comprising a second transistor of the first conductive type coupled in a diode configuration, wherein current flows according to a selected memory cell through the second transistor; a bias circuit comprising a third transistor of the first conductive type that is coupled to the first transistor by a current mirror configuration; and a differential amplifying circuit comprising a fourth transistor of the first conductive type which is coupled to the second transistor, wherein the differential amplifying circuit outputs a signal corresponding to a difference between current flowing through the third transistor and current flowing through the fourth transistor; and wherein the first transistor, the second transistor, the third transistor and the fourth transistor are comprised of one predetermined sized unit transistor element of the first conductive type, or are comprised of parallel couplings of predetermined sized unit transistor elements of the first conductive type.