Nonvolatile Memory Command Processing for Faster Data Compaction

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Solution Overview

Problem

Existing nonvolatile memory systems face challenges in efficiently performing compaction processes to consolidate valid data across fragmented blocks, leading to inefficiencies in data organization and storage.

Innovation Solution

Incorporation of a command processing unit within each memory chip to manage data validity determination and relocation, enabling high-speed compaction by identifying and writing only valid data to free blocks, assisted by a controller and error correction processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If compaction process is performed to consolidate valid data across fragmented blocks, then storage utilization is improved, but processing time and system complexity increase

Engineering Contradiction:
Improvestorage utilizationVSAvoidprocessing time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The compaction process is divided into two phases: a parallel reading phase where multiple command processing units simultaneously read data from different blocks, and a sequential writing phase where valid data is consolidated. This segmentation allows efficient utilization of parallel hardware resources during reading while maintaining manageable processing complexity during writing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The command processing units perform preliminary actions by reading and validating data from multiple blocks in parallel before the actual compaction writing begins. This preliminary reading and validity determination enables the system to prepare valid data for consolidation without blocking subsequent write operations.

Inventive Principle:
Principle #10Preliminary action

2Speed

If command processing unit is added to each memory chip to enable high-speed compaction, then compaction speed is improved, but device complexity increases

Engineering Contradiction:
Improvecompaction speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The command processing unit integrated in each memory chip performs multiple functions including data reading, validity determination, and coordination with the controller. This multi-functionality consolidates what would otherwise require separate dedicated components, achieving high-speed compaction while limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

Each command processing unit autonomously determines the validity of read data and manages local compaction operations without requiring constant controller intervention. This self-service capability enables high-speed parallel compaction operations while distributing complexity across multiple independent units rather than concentrating it in a single controller.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If validity determination is performed for each read data to identify valid data for compaction, then compaction accuracy is improved, but processing overhead increases

Engineering Contradiction:
Improvecompaction accuracyVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The command processing units continuously perform validity determination on read data as part of their normal operation, rather than performing it as a separate batch process. This continuous action integrates validity checking into the data reading workflow, maintaining high accuracy while minimizing additional processing overhead through efficient pipeline integration.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS12436878B2Nonvolatile memory, memory system, and control method of nonvolatile memory with command processing unit
Publication Date: 2025.10.07 KIOXIA CORP
  • US12436878B2 patent drawing
  • US12436878B2 patent drawing
  • US12436878B2 patent drawing

AI summary

According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.