Nonvolatile Memory Data Recovery During Power Loss
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Solution Overview
Problem
Non-volatile memory systems face challenges in ensuring data integrity during power loss, particularly during fine programming operations, where incomplete data states can lead to data loss due to the lack of separate buffering and the inability to recover accurately from intermediate states.
Innovation Solution
The implementation of a method that prepares for power loss by reading and combining partial data from non-volatile memory cells with data latches to achieve complete logical page recovery, storing this data in a safe format before power loss, allowing for data access after power restoration, utilizing a scheme that alternates between MLC and QLC programming to mitigate errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine programming is performed to store more data in non-volatile memory cells, then storage capacity is improved, but data integrity during power loss deteriorates
Solution Approach 1:
The system performs preliminary actions by reading partially programmed data from non-volatile memory cells and combining it with latched data before power loss occurs. This preparation ensures that complete data can be recovered even though the fine programming operation was interrupted, thus resolving the contradiction between storing more data and maintaining data integrity during power loss.
Solution Approach 2:
The system creates a copy of the partially programmed data by reading it from the non-volatile memory cells and combining it with the data stored in latches. This copying mechanism allows the system to reconstruct the complete data without requiring the original fine programming operation to complete successfully, thereby maintaining data integrity while enabling high storage capacity.
2Reliability
If data is read and combined from non-volatile memory cells and latches during power loss, then data recovery capability is improved, but operation complexity increases
Solution Approach 1:
The system merges the data reading operation from non-volatile memory cells with the data combination operation in the latches into a unified process. By combining these operations, the system achieves data recovery capability without proportionally increasing operation complexity, as the same circuitry performs both reading and combining functions.
Solution Approach 2:
The control circuit is designed with multi-functionality, serving both as a controller for normal programming operations and as a data recovery mechanism during power loss. This universal design allows the system to improve data recovery capability without adding separate dedicated hardware, thus avoiding excessive complexity increase.
3Loss of information
If partial data is read and combined to form complete logical pages, then data completeness is improved, but time consumption increases
Solution Approach 1:
The system performs preliminary reading of partially programmed data from non-volatile memory cells during the normal programming operation, before power loss occurs. By completing this preliminary action in advance, the system minimizes the time required for data recovery after power restoration, as the data is already read and ready for combination with latched data.
Solution Approach 2:
The data recovery process continues seamlessly after power restoration by combining the previously read partial data with the data in latches to form complete logical pages. This continuous operation ensures that data completeness is achieved without significant time interruption, as the combination process occurs immediately upon power restoration without requiring re-reading or re-processing.
Data Source
AI summary
An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.