Nonvolatile Memory Deep Standby Circuit Segmentation

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Solution Overview

Problem

Nonvolatile memory devices, particularly MRAM, face challenges with power-wasting standby currents when in standby mode, leading to increased power consumption.

Innovation Solution

The implementation of a nonvolatile memory device with control logic that includes a deep standby mode circuit, which operates in a deep standby mode requiring less standby current than conventional modes, thereby reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If a normal standby mode circuit is used, then the memory device can maintain basic standby functionality, but power consumption increases due to higher leakage currents

Engineering Contradiction:
Improvestandby power consumptionVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The standby mode circuit is segmented into two distinct circuits: a normal standby mode circuit for basic standby operations and a deep standby mode circuit for low-power operations. This segmentation allows the system to select the appropriate circuit based on power requirements, resolving the contradiction between power consumption and functional capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between normal standby mode circuit and deep standby mode circuit based on operational requirements. The control logic enables transition between modes, allowing the circuit configuration to adapt to changing power demands and functional requirements, thus resolving the static contradiction between power consumption and circuit capability.

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If the layout areas of elements in standby mode circuit are reduced, then power consumption decreases, but circuit functionality may be compromised

Engineering Contradiction:
Improveleakage currentVSAvoidcircuit operational reliability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The circuit is divided into two versions with different element sizes: a normal standby mode circuit with larger element areas for full functionality and a deep standby mode circuit with smaller element areas for reduced leakage. This segmentation allows each circuit version to be optimized for its specific operational context, resolving the contradiction between power consumption and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different layout qualities are applied to different circuits: the normal standby mode circuit uses larger element areas for reliable operation, while the deep standby mode circuit uses smaller element areas to minimize leakage current. This local differentiation of quality allows each circuit to perform optimally in its designated mode, resolving the contradiction between power loss and reliability.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12237005B2Nonvolatile memory devices that support enhanced power saving during standby modes
Publication Date: 2025.02.25 SAMSUNG ELECTRONICS CO LTD
  • US12237005B2 patent drawing
  • US12237005B2 patent drawing
  • US12237005B2 patent drawing

AI summary

A nonvolatile memory device includes a memory cell array having nonvolatile memory cells therein, which are electrically connected to a plurality of word lines and a plurality of bit lines. A write driver and row decoder are provided, which are electrically connected to the plurality of bit lines and the plurality of word lines, respectively. Control logic is configured to transfer a first voltage to the write driver and a second voltage to the row decoder. The control logic includes: (i) a normal standby mode circuit configured to operate in a normal standby mode, and (ii) a deep standby mode circuit configured to operate in a deep standby mode. To save power, the layout areas of a plurality of elements within the deep standby mode circuit are smaller than layout areas of elements within the normal standby mode circuit, so that current flowing within the deep standby mode circuit during the deep standby mode is less than current flowing within the normal standby mode circuit during the normal standby mode.