Non-volatile Memory Device Vertical Stacking Integration
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Solution Overview
Problem
Non-volatile memory devices with a multilayer structure face challenges in connecting and selecting memory cells across layers, leading to increased manufacturing costs and complexity, while conventional monolayer structures limit integration and data processing capacity.
Innovation Solution
A non-volatile memory device design featuring a first electrode with a semiconductor and integrated junction diodes, and a second electrode with pairs of junction diodes on both sides, allowing for data storage layers at intersections, facilitating vertical stacking and improved integration with a method involving tilt ion implantation for doped region formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multilayer structure is used to increase integration degree, then memory capacity and data processing capacity are improved, but device complexity and manufacturing cost increase due to difficulty in connecting and selecting memory cells across layers
Solution Approach 1:
The patent transitions from planar 2D electrode arrangements to a 3D vertical stacking configuration where first and second electrodes are positioned at different heights. Memory cells are formed at intersections across multiple layers, enabling vertical integration. This dimensional change allows multiple memory cells to be stacked above a single bit line, increasing storage capacity without proportionally increasing interconnection complexity.
Solution Approach 2:
The patent implements a nested structure where memory cells are vertically stacked with multiple data storage layers positioned at different heights between the same pair of first and second electrodes. This nesting approach allows multiple memory cells to share common electrode structures, reducing the number of separate interconnections needed compared to horizontal expansion.
2Productivity
If a multilayer structure is used to increase integration degree, then memory capacity is improved, but manufacturing cost increases due to additional manufacturing processes
Solution Approach 1:
The patent forms all data storage layers and junction diodes before establishing the final electrode connections. The junction diodes are created within the electrode structures during the same manufacturing sequence, rather than requiring separate post-assembly bonding steps. This preliminary formation of storage elements simplifies the overall fabrication process.
Solution Approach 2:
The patent combines the formation of junction diodes and data storage layers into a single integrated manufacturing sequence. The doped regions forming junction diodes are created within the electrode material during the same implantation and annealing processes used to form the data storage layer interfaces, reducing the total number of discrete manufacturing steps.
3Ease of manufacture
If conventional monolayer structure is used, then manufacturing process is simple, but integration degree and device volume efficiency are limited
Solution Approach 1:
The patent extends the conventional planar memory structure into the vertical dimension by stacking multiple data storage layers between the same electrode pairs. This allows the memory device to utilize three-dimensional space efficiently, increasing storage capacity per unit footprint while maintaining compatibility with standard semiconductor fabrication processes that can handle vertical layer formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration density, reduces device volume, and lowers manufacturing costs by simplifying the structure and enabling efficient data storage and retrieval in a multilayer setup, suitable for high-capacity semiconductor products.
Implementation Method 1
forming the at least one junction diode may include forming at least one doped region of a second conductive type opposite to the first conductive type in the semiconductor. The at least one doped region may be formed by selectively implanting impurities of the second conductive type into the semiconductor.
Data Source
AI summary
Provided are a non-volatile memory device that may be configured in a stacked structure and may be more easily highly integrated, and a method of fabricating the non-volatile memory device. At least one first electrode and at least one second electrode are provided. The at least one second electrode may cross the at least one first electrode. At least one data storage layer may be at an intersection between the at least one first electrode and the at least one second electrode. Any one of the at least one first electrode and the at least one second electrode may include at least one junction diode connected to the at least one data storage layer.