Non-volatile Memory Device with Disagreement Bit Counting
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Solution Overview
Problem
Non-volatile memory devices with resistance-change elements face challenges in implementing a fail bit count scheme similar to NAND-type flash memory, due to differences in programming methods, particularly in direct rewrite capabilities and cell threshold usage.
Innovation Solution
A non-volatile memory device with a memory cell array, cache circuits for holding program and preprogrammed data, a judging circuit for comparing data, a fail bit counting circuit to count disagreement bits, and a sequence controller to control programming sequences based on the comparison results, enabling efficient data programming and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fail bit count scheme from NAND-type flash memory is applied to ReRAM, then programming verification can be performed, but the scheme cannot be used directly due to different programming methods and direct rewrite capabilities
Solution Approach 1:
The patent segments the programming verification process into distinct phases: pre-programming data reading, disagreement bit counting, and programming sequence control. This segmentation allows the fail bit count scheme to be adapted to ReRAM's unique programming methods by dividing the verification into manageable steps that can accommodate direct rewrite capabilities and cell threshold differences
Solution Approach 2:
The patent changes the verification parameters by counting disagreement bits between pre-programmed data and programmed data instead of using conventional fail bit counting. This parameter change enables the scheme to work with ReRAM's resistance-change mechanism and direct rewrite capability, resolving the incompatibility with NAND-type flash memory methods
2Adaptability or versatility
If direct rewrite is enabled in ReRAM, then programming flexibility is improved, but the conventional fail bit count scheme becomes inapplicable
Solution Approach 1:
The patent performs preliminary action by reading pre-programmed data before the actual programming operation. This allows the system to know the expected state of memory cells in advance, enabling disagreement bit counting that works with direct rewrite operations while maintaining data integrity verification
Solution Approach 2:
The patent implements feedback by comparing programmed data with pre-programmed data to count disagreement bits. This feedback mechanism provides reliability information about the programming operation's success, allowing the system to verify data integrity even when direct rewrite is enabled
3Quantity of substance
If memory cells are three-dimensionally stacked to increase capacity, then storage density is improved, but the complexity of data programming and verification increases
Solution Approach 1:
The patent creates a universal programming verification mechanism that works across all vertically stacked memory cell layers. The disagreement bit counting and fail bit count circuits serve multiple functions: verifying programming accuracy, handling direct rewrite operations, and working with three-dimensional cell arrays, thereby reducing overall system complexity despite increased capacity
Data Source
AI summary
A non-volatile memory device including: a memory cell array storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the cell array; a second cache circuit configured to hold preprogrammed data read from an area of the cell array; and a judging circuit configured to compare and check the program data with the preprogrammed data, and judge whether there are one or more disagreement bits therebetween or not.