Nonvolatile Memory Module Dual-Mode ECC for Speed and Data Retention
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high memory capacity, speed, and low power consumption while maintaining data integrity, particularly in volatile memory devices that require frequent refresh operations.
Innovation Solution
A memory system comprising a nonvolatile memory module and a memory controller that operates in either a memory mode or a storage mode, with integrated error check and correction (ECC) mechanisms to ensure data reliability, including both external and internal ECC operations to handle data transmission and storage errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory devices are used to achieve high operation speed, then speed is improved, but data loss occurs when power is off and frequent refresh operations are required
Solution Approach 1:
The memory device dynamically switches between volatile memory mode (for high-speed operation) and nonvolatile memory mode (for data retention). The controller can change the operational state of memory cells between DRAM and flash memory modes, allowing the system to optimize between speed and reliability based on current needs
Solution Approach 2:
The patent changes the electrical parameters (voltage and resistance) of memory cells to transition between volatile and nonvolatile states. By adjusting voltage levels and resistance characteristics, the same physical memory cell can function as either DRAM or flash memory, resolving the contradiction between speed and data retention
2Reliability
If nonvolatile memory devices are used to maintain data when power is off, then data retention is improved, but operation speed decreases
Solution Approach 1:
The memory system dynamically transitions between nonvolatile storage mode and volatile memory mode. When high-speed operation is needed, the controller switches active memory cells to DRAM mode, while maintaining data retention capability through flash memory mode when power is off or during standby states
3Device complexity
If a single ECC operation is performed, then device complexity is reduced, but data integrity cannot be ensured under varying operation modes
Solution Approach 1:
The patent implements a universal ECC mechanism that can operate in multiple modes. The same ECC circuit performs both first ECC operations (for data transmitted to/from the memory device) and second ECC operations (for data stored within the memory device), adapting its functionality based on the current operation mode (volatile or nonvolatile) without requiring separate dedicated ECC circuits for each mode
Data Source
AI summary
A memory system includes a nonvolatile memory module and a memory controller. The nonvolatile memory module includes a plurality of memory chips and a module controller disposed on a printed circuit board. The module controller controls operations of the plurality of memory chips. Each of the plurality of memory chips includes a plurality of nonvolatile memory cells and operates in an operation mode. The operation mode is either a memory mode or a storage mode. The memory controller performs a write operation and a read operation on the nonvolatile memory module, and performs a first error check and correction (ECC) operation on data communicated with the nonvolatile memory module. One of the module controller or the plurality of memory chips performs a second ECC operation on data stored in the plurality of memory chips based on the operation mode of the plurality of memory chips.