Nonvolatile Memory Dual-Plane Read Voltage Adaptation

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Solution Overview

Problem

Nonvolatile memory devices with a multi-plane structure face challenges in performing simultaneous read operations on planes with different program states, particularly when the Most Significant Bit (MSB) program operation is not uniformly applied across both planes.

Innovation Solution

A method for operating a nonvolatile memory device that receives a dual plane read command, checks the MSB program state of each plane using flag cells, and adjusts the read voltage accordingly to ensure simultaneous reading by resetting or using alternative voltages based on the program states of the planes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a read operation is performed on two planes at the same time, then the reading speed is improved, but the read operation can only be performed when both planes have the same program state

Engineering Contradiction:
Improvereading speedVSAvoidread operation compatibility
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The controller performs a preliminary check of the MSB program state of each plane before executing the dual plane read operation. Based on the check result, the controller determines whether to proceed with simultaneous reading or to perform separate reading operations, thereby preventing read errors while maintaining high speed when conditions permit

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The read operation mode is dynamically adjusted based on the program states of the two planes. When both planes have the same MSB program state, dual plane simultaneous reading is executed for high speed. When program states differ, the system switches to separate reading operations to ensure data integrity

Inventive Principle:
Principle #15Dynamics

2Speed

If the read operation is performed on two planes with different program states, then the reading speed is improved, but read errors occur

Engineering Contradiction:
Improvereading speedVSAvoiddata reading accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

Before performing the dual plane read operation, the controller checks the MSB program state of each plane to determine compatibility for simultaneous reading. This preliminary verification ensures that read operations are only performed when both planes have matching program states, preventing read errors while maintaining high speed when conditions allow

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from the program state check to control the execution of the read operation. Based on whether the MSB program states match, the controller either proceeds with dual plane simultaneous reading or switches to separate reading operations, thereby ensuring data accuracy while optimizing reading speed

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8270219B2Method of operating nonvolatile memory device capable of reading two planes
Publication Date: 2012.09.18 SK HYNIX INC
  • US8270219B2 patent drawing
  • US8270219B2 patent drawing
  • US8270219B2 patent drawing

AI summary

A nonvolatile memory device is operated by receiving a dual plane read command for simultaneously reading first and second planes, each comprising memory cells, receiving an MSB read address for reading data stored in the memory cells, checking whether an MSB program operation has been performed on each of the first and second planes, and performing the read operation on the first and second planes according to a result of the check and outputting the read data.