Nonvolatile Memory Cell With Dual Wells For Efficient Erase
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Solution Overview
Problem
Existing nonvolatile memory technologies face challenges in effectively erasing data due to difficulties in inverting the electric field polarity of the floating gate electrode, leading to one-time programmable memory limitations and reduced write performance.
Innovation Solution
The introduction of a semiconductor device structure with an n-type second semiconductor region and a selection transistor, along with an electric charge storage portion having a floating gate electrode, allows for independent control of the electric field, enabling efficient electron discharge and data erasure through a positive voltage application to the second semiconductor region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the electric field of the floating gate electrode is controlled by coupling capacitance between it and a well formed in the substrate, then the structure is simplified and manufacturing is facilitated, but it is difficult to invert the polarity of the electric field and electrons cannot be effectively extracted
Solution Approach 1:
The patent divides the control mechanism into two independent parts: a first well for electron injection and a second well for electron extraction. This segmentation allows each well to be independently controlled, enabling flexible polarity inversion of the electric field while maintaining the simple single-layer floating gate structure. The segmentation resolves the contradiction by providing operational flexibility without increasing structural complexity.
Solution Approach 2:
The patent introduces a second well as an intermediary structure that mediates the extraction of electrons from the floating gate electrode. This intermediary element enables the inversion of electric field polarity by providing an additional pathway for charge control, allowing electrons to be extracted through the second well while maintaining the original simple structure for manufacturing.
2Ease of manufacture
If a single-layer conductor film is used for the floating gate electrode, then the manufacturing process is facilitated and fabrication yield is enhanced, but electrical erasing is impossible and the memory becomes one-time programmable
Solution Approach 1:
The patent segments the charge control function into two independent wells (first well for writing, second well for erasing) that work with the single-layer floating gate electrode. This segmentation enables the simple single-layer structure to achieve both write and erase operations, resolving the contradiction between manufacturing simplicity and functional versatility.
Solution Approach 2:
The patent makes the single-layer floating gate electrode multi-functional by enabling it to perform both electron injection (write operation via first well) and electron extraction (erase operation via second well). This multi-functionality allows the simple single-layer structure to support reversible programming operations, enhancing adaptability without complicating the manufacturing process.
3Reliability
If electrons are accumulated in the floating gate electrode for write operation, then data is stored, but the negative own electric field produced makes further electron injection difficult and write performance degrades
Solution Approach 1:
The patent extracts the electron accumulation function from the traditional single control mechanism and distributes it between two wells. The first well handles electron injection for writing, while the second well is available to extract electrons for erasing. This extraction capability resolves the contradiction by providing a dedicated pathway to remove the negative electric field effect after writing, enabling efficient subsequent operations.
Solution Approach 2:
The patent inverts the traditional approach by providing a dedicated second well specifically for electron extraction rather than relying on the same structure used for injection. This inversion allows the system to actively remove electrons from the floating gate electrode, counteracting the negative own electric field and restoring write capability for high-speed repetitive operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of nonvolatile memory by enabling effective data erasure and improved write operations, overcoming the limitations of one-time programmable memory and enhancing the overall performance of semiconductor devices.
Implementation Method 1
Control of an electric field for injecting electric charges into a floating gate electrode is carried out by, for example, the coupling capacitance between a well formed in a substrate and the floating gate electrode or the like.
Implementation Method 2
the state of electric charges of this floating gate electrode manifests itself as change in threshold voltage
Data Source
AI summary
The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.