Nonvolatile Memory Read Test Accuracy via Dummy Cell Current Replication
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Solution Overview
Problem
Existing read operation tests for nonvolatile semiconductor memory devices are inaccurate, leading to degradation in yield and reliability due to the inability to accurately replicate the actual data readout operation, resulting in erroneous judgments of defective or non-defective products.
Innovation Solution
Incorporating dummy cell transistors coupled in parallel with bit lines and a current generating circuit that supplies a test current, allowing the sense amplifier to compare the test current with a reference current, thereby replicating the rise in ON cell current similar to actual data readout operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If short-time writing or erasing is carried out to simulate cell deterioration, then the test can account for cell deterioration, but the test time increases due to repeated operations
Solution Approach 1:
The patent pre-calculates and stores the relationship between write/erase cycle counts and threshold voltage changes in a lookup table before testing. During the actual test, the system only needs to perform a single read operation and compare it against pre-computed deterioration models, eliminating the need for repeated write/erase cycles during testing.
Solution Approach 2:
The patent creates a mathematical model (copy) of cell deterioration behavior based on write/erase cycle effects. Instead of physically repeating deterioration processes during testing, the system uses this modeled copy to predict threshold voltage at different cycle counts, achieving the same testing goal much faster.
2Reliability
If the threshold voltage is adjusted to simulate deteriorated state, then cell deterioration can be tested, but manufacturing precision decreases due to production tolerance variations
Solution Approach 1:
The patent changes the approach from directly controlling threshold voltage (which is affected by manufacturing tolerances) to controlling the number of write/erase cycles. The lookup table stores threshold voltage values corresponding to different cycle counts, allowing the system to simulate deterioration through cycle counting rather than direct voltage adjustment, thereby avoiding manufacturing precision issues.
3Measurement precision
If point-by-point checking of ON cell current is performed, then accurate deterioration simulation is achieved, but test complexity increases
Solution Approach 1:
The patent implements a continuous testing approach where the system performs a single read operation and uses pre-stored lookup table data to evaluate deterioration effects across the entire range of write/erase cycles. This eliminates the need for repeated point-by-point measurements, maintaining measurement precision while dramatically simplifying the test procedure.
Data Source
AI summary
A nonvolatile semiconductor memory device includes: a sense amplifier; bit lines coupled to the sense amplifier; memory cell transistors and dummy cell transistors coupled in parallel with the bit lines; and a current generating circuit that supplies a test current to current nodes. Either of the source and the drain of each of the dummy cell transistors is coupled to a bit line and the other is coupled to a current node. In a read operation test, the current generating circuit is activated and then the dummy cell transistors are turned on. The sense amplifier compares the test current passed through a bit line with a reference current and outputs output data corresponding to the result of the comparison.