Non-volatile Memory Device with Dummy Cells for Side-Channel Leakage Reduction
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Solution Overview
Problem
Current non-volatile memory devices are vulnerable to side-channel attacks, which can compromise the security of encryption keys by analyzing side-channel leakage such as power consumption and electromagnetic waves, despite existing countermeasures like PUF techniques facing issues with reproducibility and uniqueness under environmental variations.
Innovation Solution
A non-volatile memory device with a memory group of variable resistance cells, including data and dummy cells, where dummy data is recorded to reduce correlation between side-channel leakage and information data, and PUF data is used to enhance tamper resistance, utilizing resistance variations for secure key storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encryption keys are stored in non-volatile memory, then security requirements are met, but the device becomes vulnerable to side-channel attacks
Solution Approach 1:
The patent introduces dummy cells as intermediary elements between the data cells and the external environment. These dummy cells act as a mediator that absorbs side-channel leakage, preventing direct correlation between power consumption patterns and the actual encryption keys stored in data cells. The dummy cells serve as a buffer layer that disrupts the attack vector without affecting the security of the actual data.
Solution Approach 2:
The patent changes the parameter of memory cell resistance by introducing dummy cells with different resistance characteristics. By varying the resistance values in dummy cells and adjusting their proportion within the memory group, the patent modifies the overall side-channel leakage profile. This parameter change makes it difficult for attackers to extract meaningful information from power consumption patterns while maintaining normal encryption key storage functionality.
2Reliability
If dummy cells are added to reduce side-channel leakage, then tamper resistance improves, but device complexity increases
Solution Approach 1:
The patent merges the functionality of data storage and side-channel protection into a single memory group structure. Instead of adding separate protective circuits or layers, the dummy cells are integrated directly into the memory array alongside data cells. This merging approach allows the system to achieve tamper resistance while maintaining a relatively simple and unified memory architecture that can be implemented using standard manufacturing processes.
3Adaptability or versatility
If PUF data is used for device-specific security, then uniqueness is improved, but reproducibility under environmental variations deteriorates
Solution Approach 1:
The patent changes the physical parameters of the memory cells by controlling their resistance values to specific ranges. By setting dummy cell resistances to differ from data cell resistances and adjusting the proportion of dummy cells, the patent creates stable, reproducible side-channel leakage patterns that are consistent across environmental variations. This parameter control ensures that PUF-based security features remain reliable while maintaining device-specific uniqueness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances tamper resistance by minimizing the likelihood of information data estimation from side-channel leakage and ensuring high security through device-specific PUF data, even under environmental influences.
Implementation Method 1
a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value
Data Source
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AI summary
A non-volatile memory device (10) includes: a memory group of a plurality of variable resistance memory cells (21) in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit (11) which performs, in parallel, a read operation on each of the plurality of memory cells (21) included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit (11) and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.