Nonvolatile Memory Dummy Gate Width Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D nonvolatile memory devices with vertically stacked memory cells face issues such as abnormal program operations and reduced channel current due to the coupling between dummy floating gate electrodes and control gate electrodes, particularly at the uppermost and lowermost positions.
Innovation Solution
The design minimizes the size of dummy floating gate electrodes by positioning them with a smaller width parallel to the substrate, reducing the coupling ratio with control gate electrodes, and includes a method for fabricating this structure through alternating layers of interlayer dielectric materials with varying etch rates to form grooves and deposit charge blocking and floating gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy floating gate electrodes are formed at the uppermost and lowermost parts of the stack structure with the same width as intermediate floating gate electrodes, then the structure is simple to manufacture, but the coupling ratio between dummy floating gate electrodes and control gate electrodes increases causing abnormal program operations and reduced channel current
Solution Approach 1:
The patent applies local quality by making the dummy floating gate electrodes at the uppermost and lowermost parts have a different width (smaller width in the first direction) compared to intermediate floating gate electrodes. This local structural variation reduces the coupling ratio between dummy floating gate electrodes and control gate electrodes, preventing abnormal program operations and maintaining channel current, while maintaining overall structural simplicity.
2Reliability
If the width of dummy floating gate electrodes is reduced to minimize coupling ratio, then abnormal program operations are prevented and channel current is maintained, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the width parameter of dummy floating gate electrodes at the uppermost and lowermost parts, making them smaller in the first direction compared to intermediate floating gate electrodes. This parameter modification reduces the coupling ratio and prevents operational abnormalities. The etch rate differences between first/third interlayer dielectric layers and second interlayer dielectric layer enable precise control of this width parameter during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents abnormal program operations and maintains channel current during read operations by reducing the area of contact between dummy floating gate electrodes and control gate electrodes, thereby enhancing the operational characteristics of the nonvolatile memory device.
Implementation Method 1
the first and third interlayer dielectric layers have a lower etch rate than plurality of the second interlayer dielectric layer
Data Source
AI summary
A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.