Nonvolatile Memory Dummy Cells Reduce Read Disturbance
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Solution Overview
Problem
Flash memory devices experience data distortion due to soft programming, where repeated read operations cause unintended shifts in memory cell threshold voltages, leading to read-out disturbances, especially as device features become smaller and more densely integrated.
Innovation Solution
A nonvolatile memory device with a memory cell array and a row selection circuit, utilizing dummy memory cells and voltage generators to apply specific read-out voltages during operations, where dummy read-out voltages are lower than the read-out voltage applied to unselected wordlines, reducing floating gate coupling and minimizing threshold voltage shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy memory cells are added to the memory cell array, then read-out disturbance is reduced, but device complexity increases
Solution Approach 1:
The memory cell array is segmented to include dedicated dummy memory cells (first and second dummy memory cells) separated from the functional memory cells. These dummy cells are positioned at specific locations within the NAND string to absorb floating gate coupling effects, thereby protecting the functional memory cells from read-out disturbance while maintaining their operational integrity.
Solution Approach 2:
Dummy memory cells act as intermediary elements between the read operation and the functional memory cells. By applying dummy read-out voltages to these intermediary cells, the harmful floating gate coupling is absorbed or neutralized before it can affect the stored data in the functional memory cells, thus serving as a protective buffer.
2Object-affected harmful factors
If different dummy read-out voltages are applied to first and second dummy wordlines, then floating gate coupling is reduced, but voltage control complexity increases
Solution Approach 1:
Different dummy read-out voltages are applied to different dummy wordlines (first dummy wordline and second dummy wordline) based on their specific positions and coupling characteristics within the memory cell array. This localized voltage approach optimizes the reduction of floating gate coupling for each specific dummy cell location, accounting for variations in electric field distribution and coupling strength.
Solution Approach 2:
The voltage parameters (dummy read-out voltages) are specifically adjusted and optimized for different dummy wordlines. By changing the voltage levels applied to different dummy cells, the system effectively controls and minimizes floating gate coupling effects without requiring complex additional control mechanisms beyond standard voltage generation capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the accuracy and reliability of read-out operations by reducing floating gate coupling and threshold voltage shifts, thereby minimizing data distortion and maintaining data integrity in flash memory devices.
Implementation Method 1
the first and second dummy read-out voltages having respective first and second voltage levels and the read-out voltage having a third voltage level greater than the first and second voltage levels... reducing floating gate coupling on a wordline adjacent to the first or second dummy wordline due to a shift in a threshold voltage of the first or second dummy memory cell
Data Source
AI summary
A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.