Nonvolatile Memory Error Correction via Dynamic Reference Selection

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Solution Overview

Problem

Conventional error correction techniques in nonvolatile memories require larger numbers of bits and die size to correct errors, limiting their effectiveness, especially in advanced memory cell configurations.

Innovation Solution

The use of multiple reference signals during data reading to select the best reference value for error correction, improving the capability to detect and correct errors in nonvolatile memories, including multi-level memory cells, without increasing the number of bits or die size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional error correction techniques are used, then error correction capability is provided, but the number of bits and die size must be increased

Engineering Contradiction:
Improveerror correction capabilityVSAvoidnumber of bits
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent changes the parameter of reference values used during data reading. By using multiple reference values (first reference value, second reference value, third reference value) instead of a single fixed reference, the system improves error detection and correction capability without increasing the number of bits. The sensing circuit compares read data against multiple reference values to determine the most accurate data interpretation, thereby enhancing reliability while maintaining bit efficiency.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional error correction techniques are used, then error correction capability is provided, but the die size must be increased

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddie size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent modifies the parameter of reference values in the sensing circuit. By implementing multiple reference values (first reference value, second reference value, third reference value) that can be selectively used during data reading, the system achieves enhanced error correction capability without requiring additional bits that would increase die size. This parameter-based approach allows the same physical footprint to provide superior error correction performance.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If multiple reference values are used for reading data, then error detection and correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror detection and correction capabilityVSAvoidsensing circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces dynamic selection of reference values based on reading conditions. The sensing circuit dynamically chooses which reference value (first, second, or third) to use when reading data from memory cells. This dynamic approach allows the system to adapt to different reading scenarios and optimize error correction performance without requiring all possible reference value combinations to be processed simultaneously, thereby managing complexity effectively.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent segments the reference values into distinct categories (first reference value, second reference value, third reference value) that can be independently selected and processed. By dividing the reference value space into manageable segments, the sensing circuit can systematically evaluate each segment's suitability for current reading conditions, improving error detection capability while maintaining manageable circuit complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260050511A1Systems, methods, and devices for error correction in nonvolatile memories
Publication Date: 2026.02.19 INFINEON TECHNOLOGIES LLC
  • US20260050511A1 patent drawing
  • US20260050511A1 patent drawing
  • US20260050511A1 patent drawing

AI summary

Systems, methods, and devices provide error correction in such nonvolatile memories. Methods include identifying a read operation associated with a nonvolatile memory array, performing a plurality of sensing operations on the nonvolatile memory array, the plurality of sensing operations comprising a plurality of comparisons between sensed values and reference values, and generating a plurality of data outputs based on the plurality of sensing operations. Methods further include generating a plurality of results based on the plurality of data outputs, wherein each of the plurality of results identifies a number of errors associated with at least one of the plurality of data outputs, and selecting a data output of the plurality of data outputs based, at least in part, on the identified number of errors.