Nonvolatile Memory Dynamic Verification Mode Selection
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Solution Overview
Problem
Nonvolatile memory systems face challenges in balancing programming speed and accuracy, particularly in multi-level memory cells, due to the complexity of managing threshold voltage distributions and the wear caused by repeated programming and erase operations.
Innovation Solution
The method involves dynamically selecting between different verification modes based on the programming condition of memory cells, applying either a bit line forcing voltage or a bit line program voltage, and using control logic to manage the programming process, thereby optimizing the number of programming intervals and reducing wear on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a bit line forcing voltage is applied to all memory cells during programming, then programming speed is improved, but programming accuracy deteriorates for slow memory cells
Solution Approach 1:
The patent applies different bit line voltages to different memory cells based on their programming speed characteristics. Fast memory cells receive a bit line forcing voltage (e.g., 0V) for rapid programming, while slow memory cells receive a bit line program voltage (e.g., 5V) for accurate programming. This local differentiation resolves the contradiction by optimizing voltage application according to each cell's specific needs rather than using a uniform approach.
Solution Approach 2:
The patent dynamically adjusts the bit line voltage during the programming process based on real-time evaluation of programming conditions. The control logic monitors programming progress and switches between forcing voltage and program voltage modes as needed, allowing the system to adapt to the actual state of memory cells and achieve both speed and accuracy.
2Manufacturing precision
If multiple programming intervals are executed to ensure programming accuracy, then programming accuracy is improved, but the useful life of memory cells deteriorates due to increased wear
Solution Approach 1:
The patent applies different programming strategies to fast and slow memory cells. Fast memory cells require fewer programming intervals and less verification, while slow memory cells receive additional programming intervals with appropriate voltage levels. This localized approach ensures that only the necessary number of programming operations are performed on each cell, minimizing wear while maintaining accuracy.
Solution Approach 2:
The patent implements a verification mechanism that evaluates programming conditions after each programming interval. Based on the verification results, the control logic determines whether additional programming is needed. This feedback loop prevents unnecessary programming intervals, reducing wear on memory cells while ensuring that programming accuracy requirements are met.
3Ease of operation
If traditional verification modes are used for all memory cells, then verification simplicity is maintained, but programming accuracy deteriorates for slow memory cells
Solution Approach 1:
The patent dynamically selects verification modes based on the programming condition of memory cells. For fast memory cells, a simple verification mode is used, while for slow memory cells, a more rigorous verification mode is applied. The control logic automatically adjusts the verification strategy based on real-time programming status, maintaining simplicity where possible while ensuring accuracy where needed.
Solution Approach 2:
The patent applies different verification strategies to different memory cells based on their programming characteristics. Fast memory cells undergo simpler verification processes, while slow memory cells receive more thorough verification with appropriate voltage levels and multiple checks. This localized verification approach maintains overall system simplicity while ensuring high accuracy for problematic cells.
Data Source
AI summary
Nonvolatile memory devices, memory systems and related methods of operating nonvolatile memory devices are presented. During a programming operation, the nonvolatile memory device is capable of using bit line forcing, and is also capable of selecting a verification mode for use during a verification operation from a group of verification modes on the basis of an evaluated programming condition.