Nonvolatile Memory ECC Paths for Fixed and Variable Latency Access
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Solution Overview
Problem
Existing nonvolatile memory technologies face challenges in improving data retention characteristics while maintaining access performance, particularly in supporting execute-in-place (XIP) and sequential access models, as adding error correction code (ECC) features often increases latency and degrades performance.
Innovation Solution
A nonvolatile memory system with dual access modes: a first access mode with fixed latency for XIP operations and a second access mode with variable latency for sequential access, utilizing separate ECC processing paths to optimize performance and data retention without compromising access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC processing is added to NVRAM to improve data retention characteristics, then data retention is improved, but access performance is degraded due to increased latency
Solution Approach 1:
The patent segments the NVRAM system into two distinct access modes: a first access mode with fixed latency for XIP operations and a second access mode with variable latency for sequential access. Separate ECC processing paths are provided for each mode, allowing optimized ECC processing tailored to each access pattern without compromising overall performance
Solution Approach 2:
The patent implements dynamic access mode selection where the system can switch between fixed latency mode and variable latency mode based on the access pattern requirements. This dynamic approach allows the system to adapt ECC processing latency to the specific operational context, maintaining high performance for both XIP and sequential access workloads
2Speed
If fixed latency access mode is used for XIP operations, then access speed is improved, but ECC processing flexibility is reduced
Solution Approach 1:
The patent provides separate ECC processing paths: a first ECC processing path for fixed latency access mode and a second ECC processing path for variable latency access mode. Each path is optimized for its specific access pattern, allowing the system to maintain both high-speed fixed latency operation and flexible variable latency operation with appropriate ECC processing for each
3Reliability
If variable latency access mode is used for sequential access, then ECC processing capability is improved, but access speed is reduced
Solution Approach 1:
The patent implements dynamic mode selection where the system switches between fixed latency mode and variable latency mode based on access patterns. The variable latency mode with enhanced ECC processing capability is activated for sequential access workloads, while fixed latency mode is used for XIP operations, optimizing performance for each specific use case
4Reliability
If handshake protocol is implemented for fixed latency access, then access control is improved, but overhead increases reducing performance
Solution Approach 1:
The patent segments the control mechanism by providing different control approaches for different access modes. For fixed latency access mode, the system uses a simplified control protocol that omits certain handshake steps to minimize overhead and maintain high performance, while still ensuring proper access control. For variable latency mode, more comprehensive handshake protocols can be used
Data Source
AI summary
Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode.