Nonvolatile Memory Erase Method with Temperature-Adaptive Delay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile memory devices face issues with erase failures due to temperature variations affecting the threshold voltage of ground selection transistors, leading to inefficient erase operations.
Innovation Solution
A method for a nonvolatile memory device that involves applying an erase voltage to a substrate and a ground voltage to a ground selection line, with a delay time set based on the temperature of the memory cell array, ensuring the ground selection line voltage increases faster than the substrate voltage, thereby preventing erase failures by maintaining a stable threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If erase voltage is applied to the substrate during erase operation, then erase operation is performed, but threshold voltage of ground selection transistor varies due to temperature changes causing erase failure
Solution Approach 1:
The patent applies ground voltage to the ground selection line before applying erase voltage to the substrate, and maintains it during a delay time period. This preliminary action prepares the ground selection transistor to withstand the subsequent erase operation, preventing threshold voltage variation and erase failure caused by temperature changes.
Solution Approach 2:
The patent changes the voltage parameter of the ground selection line from ground voltage to increased voltage after the delay time, based on temperature-dependent timing. This parameter change ensures the ground selection transistor remains stable throughout the erase operation despite temperature variations, preventing erase failure.
2Reliability
If ground voltage is applied to ground selection line during delay time, then threshold voltage stability is improved, but erase operation time is increased
Solution Approach 1:
The patent uses temperature-dependent delay time to dynamically adjust the duration of ground voltage application. The delay time is set based on detected temperature, allowing the ground voltage to be maintained for the precise minimum duration needed to stabilize the ground selection transistor, thereby improving threshold voltage stability without unnecessarily extending erase operation time.
3Reliability
If ground selection line voltage increases faster than substrate voltage, then erase failure is prevented, but voltage control complexity increases
Solution Approach 1:
The patent increases the ground selection line voltage after the delay time, following the preliminary application of ground voltage. This sequential voltage control ensures the ground selection transistor is properly prepared before the substrate voltage rises during erase, preventing erase failure while using a manageable voltage control sequence.
Solution Approach 2:
The patent uses temperature detection feedback to set the delay time, which determines when the ground selection line voltage is increased. This feedback mechanism allows the voltage control to adapt to temperature conditions, ensuring reliable erase operation without requiring overly complex voltage control circuits.
Data Source
AI summary
An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time.