Nonvolatile Memory Erase Loop Verification for Data Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Highly integrated nonvolatile memory devices and storage devices face reliability issues due to data corruption, which is exacerbated by their miniaturization and structural changes, leading to decreased performance and accuracy in erase operations.
Innovation Solution
A nonvolatile memory device with a control logic circuit that performs iterative erase loops, including an erase section and an erase verification section, where an extra erase voltage is applied if memory cells are determined to be in an abnormal state, ensuring thorough data erasure and maintaining device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If nonvolatile memory devices are highly integrated and miniaturized, then manufacturing cost decreases and degree of integration increases, but data corruption occurs and reliability decreases
Solution Approach 1:
The patent performs preliminary verification of erase operations by checking whether memory cells have been completely erased before considering the erase operation complete. This preliminary check prevents data corruption by ensuring that no residual data remains in miniaturized memory cells, thereby maintaining reliability while working with highly integrated structures.
Solution Approach 2:
The patent implements a feedback mechanism where the result of the erase verification is used to determine whether to perform additional erase operations. If the verification indicates incomplete erasure, the system feedbacks this information and performs extra erase operations, ensuring complete data removal and preventing corruption in miniaturized memory devices.
2Device complexity
If nonvolatile memory devices are highly integrated and miniaturized, then degree of integration increases, but erase operation accuracy decreases
Solution Approach 1:
The patent performs preliminary verification checks after erase operations to ensure complete erasure of memory cells. This preliminary action compensates for the reduced accuracy in miniaturized devices by explicitly verifying that the erase operation achieved the desired result, thereby maintaining precision despite device miniaturization.
Solution Approach 2:
The patent uses feedback from erase verification results to determine whether additional erase operations are needed. This feedback loop ensures that even if the initial erase operation on miniaturized memory cells was imprecise, subsequent operations will achieve complete erasure, thereby maintaining manufacturing precision.
3Reliability
If iterative erase loops with verification are performed, then data erasure completeness improves, but operation time increases
Solution Approach 1:
The patent performs verification checks and additional erase operations only when necessary, based on the results of preliminary verification. This partial action approach ensures complete data erasure (excessive action when needed) while avoiding unnecessary operations that would waste time, thereby balancing reliability improvement with time efficiency.
Solution Approach 2:
The patent uses feedback from verification results to control the execution of additional erase operations. If verification indicates complete erasure, no further operations are performed, saving time. If verification indicates incomplete erasure, additional operations are triggered, ensuring completeness. This feedback-based control optimizes the balance between reliability and operation time.
Data Source
AI summary
A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.