Nonvolatile Memory Erase Mode Selection for Wear Reduction

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Solution Overview

Problem

Nonvolatile semiconductor memory devices face challenges in extending their lifetime and improving data reliability due to the wear and tear associated with erase operations, which can lead to reduced performance and shorter device lifespan.

Innovation Solution

A method for a nonvolatile memory device that dynamically adjusts erase times by employing multiple erase modes, including a fast erase mode and slow erase modes with varying pulse widths and voltages, allowing the memory controller to select the appropriate mode based on the access conditions and status of the write buffer, thereby minimizing stress on memory blocks and extending the device's lifespan.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fast erase mode is used to reduce erase time, then productivity is improved, but reliability deteriorates due to increased erase voltage stress on memory blocks

Engineering Contradiction:
Improveerase speedVSAvoidmemory block durability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic erase mode selection that adapts to current memory block states and system conditions. The memory controller monitors write buffer status, erase request patterns, and memory block health metrics to dynamically choose between fast erase mode (for performance when conditions permit) and slow erase mode (for reliability when memory blocks are stressed), thereby resolving the contradiction between erase speed and memory block durability

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes erase operation parameters based on monitored conditions. When memory blocks show signs of stress or degradation, the system switches from fast erase parameters (high voltage, short duration) to slow erase parameters (lower voltage, longer duration with pulsed sequences), thereby reducing erase voltage stress on deteriorating memory blocks while maintaining acceptable erase performance

Inventive Principle:
Principle #35Parameter changes

2Reliability

If slow erase mode is used to reduce voltage stress, then reliability is improved, but productivity deteriorates due to increased erase time

Engineering Contradiction:
Improvememory block durabilityVSAvoiderase speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts erase mode based on real-time monitoring of memory block health, write buffer status, and erase request patterns. When memory blocks are healthy and system conditions permit, fast erase mode is used for high productivity. When memory blocks show stress or degradation signs, the system automatically switches to slow erase mode to prioritize reliability, thereby resolving the contradiction between erase speed and memory block durability through adaptive decision-making

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If multiple erase modes are implemented to handle different conditions, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improveerase mode selection flexibilityVSAvoidcontrol logic complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory controller implements self-service monitoring and decision-making capabilities, automatically assessing memory block health status, write buffer conditions, and erase request patterns to determine the appropriate erase mode without external intervention. This self-service approach enables adaptable erase mode selection while keeping the control logic relatively simple, as the system autonomously manages the complexity of monitoring multiple parameters and making mode selection decisions

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9733864B2Memory system including nonvolatile memory device and erase method thereof
Publication Date: 2017.08.15 SAMSUNG ELECTRONICS CO LTD
  • US9733864B2 patent drawing
  • US9733864B2 patent drawing
  • US9733864B2 patent drawing

AI summary

An erase method of a nonvolatile memory device is provided which includes receiving an erase request; selecting an erase mode of a memory block corresponding to the erase request, based on an access condition of the nonvolatile memory device managed by a memory controller; and controlling the nonvolatile memory device to erase the memory block according to the selected erase mode. The erase mode includes a fast erase mode of which an erase time for the memory block is shorter than a reference time and a slow erase mode of which an erase time for the memory block is longer than the reference time.