Nonvolatile Memory Erase Control via Pulsed Voltage

The patent applies periodic pulsed voltage differences during the erase operation instead of continuous high voltage. The control circuit generates periodic pulse signals that alternately apply high voltage difference (for rapid electron discharge) and low voltage difference (to prevent fast program phenomenon). This periodic action allows the system to achieve fast erase speeds while avoiding the harmful effects of sustained high voltage differences, thereby maintaining data storage reliability.

The patent dynamically adjusts the voltage difference applied during erase operations based on the operational history of memory blocks. The control circuit monitors the number of erase cycles and automatically modulates the voltage amplitude and pulse width. For blocks requiring repeated erasure, the system applies dynamically adjusted pulsed voltages that maintain erase effectiveness while preventing the accumulation of damage that leads to invalid block formation, thus preserving data storage capacity.

The patent employs periodic pulsed voltage application where high voltage difference pulses are interspersed with low voltage intervals. During high voltage pulses, electrons are rapidly discharged from floating gates achieving complete erasure. During low voltage intervals, the system prevents slow erase phenomenon from occurring. This periodic modulation achieves both erase completeness and time efficiency by concentrating the erosive action into brief high-voltage pulses rather than sustained application.