Nonvolatile Memory Decoding for 2-3 Bit Error Correction
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Solution Overview
Problem
Current memory systems face challenges in efficiently decoding data encoded with error-correcting codes, particularly when dealing with a small number of bit errors, as they require complex calculations and larger circuit scales for error correction.
Innovation Solution
A memory system with a memory controller that calculates syndromes, estimates bit errors, and performs variable transformation on error locator polynomials to correct errors, reducing the need for multiple inverse element calculations and simplifying the decoder circuit by using a lookup table with specific key information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction decoding is performed for 2 or 3 bit errors, then error correction capability is achieved, but calculation complexity increases and circuit scale becomes larger
Solution Approach 1:
The decoding process is segmented into distinct stages: syndrome calculation, error number estimation, conditional branching based on error count, and targeted root calculation. This segmentation allows the system to handle different error scenarios efficiently without always performing the complete, complex decoding procedure, thereby reducing overall circuit complexity while maintaining error correction capability for 2 or 3 bit errors
Solution Approach 2:
The system performs preliminary error number estimation using syndrome values before committing to full error correction procedures. By estimating the number of bit errors in advance and using this information to guide subsequent decoding steps, the system avoids unnecessary complex calculations when errors are few, thus reducing calculation complexity and circuit scale while preserving reliability
2Measurement precision
If multiple inverse element calculations are performed for error locator polynomial roots, then accurate error location is achieved, but decoding time increases
Solution Approach 1:
The system performs preliminary error number estimation using syndrome values before calculating roots of the error locator polynomial. This preliminary step allows the system to determine in advance how many inverse element calculations are actually needed, avoiding unnecessary calculations and thus reducing decoding time while maintaining accurate error location through targeted root calculations
Solution Approach 2:
The decoding process dynamically adapts its complexity based on the estimated number of errors. When few errors are detected, the system performs only the necessary minimal calculations; when more errors are present, it engages more comprehensive decoding procedures. This dynamic approach optimizes the balance between error location accuracy and decoding time by adjusting computational effort to match actual error conditions
3Manufacturing precision
If complex decoding algorithms are implemented, then error correction accuracy is improved, but manufacturing complexity increases
Solution Approach 1:
The decoding algorithm is segmented into modular functional blocks: syndrome calculation unit, error number estimation unit, conditional judgment unit, and root calculation unit. Each module performs a specific, well-defined function that can be independently designed, tested, and manufactured. This modular segmentation improves error correction accuracy through systematic processing while reducing manufacturing complexity by avoiding the need to implement a single monolithic complex algorithm
Solution Approach 2:
The system implements preliminary error number estimation using relatively simple syndrome calculations before proceeding to more complex root calculation procedures. This preliminary action allows the system to achieve accurate error correction by guiding subsequent processing steps based on initial error assessment, thereby improving error correction accuracy while keeping the overall implementation manageable and easier to manufacture through staged processing
Data Source
AI summary
A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory stores data encoded by using an error correcting code for correcting n-bit errors(n is an integer of 3 or more) or less. The memory controller reads a received word from the nonvolatile memory, calculates a syndrome by using the read received word, estimates the number of bit errors by using the syndrome. When the number of bit errors is 2 or 3, the memory controller calculates an inverse element of a value calculated based on the syndrome, executes, by using the inverse element, variable transformation on a variable of an error locator polynomial corresponding to the number of bit errors and calculation of a root of a transformed polynomial obtained by transforming the error locator polynomial according to the variable transformation, executes variable inverse transformation on the root of the transformed polynomial to obtain the root of the error locator polynomial, and corrects the error in the error location corresponding to the root of the error locator polynomial.