Multi-programmable Non-volatile Memory Cell Design
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Solution Overview
Problem
The challenge is to fabricate reprogrammable non-volatile memory devices that can share processing steps and layers with other semiconductor devices on the same substrate without requiring additional layers or processing steps, as existing methods often damage thinner oxides used in logic devices or microcontrollers during program/erase cycles, limiting their cycle capability to less than a hundred cycles.
Innovation Solution
A non-volatile memory device design featuring a semiconductor body with specific well regions and a floating gate, where the floating gate spans the distance between source and drain well regions, and the second well region operates at a voltage less than the power supply voltage, allowing for programming, erasing, and reading without additional layers or processing steps, and sharing common structures and fabrication steps with other semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional layers and processing steps are used to form a floating gate for non-volatile memory, then program/erase cycle capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the control gate serve dual functions: as the control gate for the MOSFET and as the floating gate for non-volatile memory storage. This eliminates the need for a separate floating gate structure and its associated processing steps, while maintaining both logic device functionality and non-volatile memory capability with improved program/erase cycle life
Solution Approach 2:
The control gate and floating gate are merged into a single structure. The control gate is configured to function both as the control electrode for the MOSFET and as the charge storage element for non-volatile memory, combining two previously separate components into one unified structure that reduces device complexity
2Productivity
If thinner oxide layers are used for logic devices, then device integration is improved, but program/erase cycle capability deteriorates due to oxide damage
Solution Approach 1:
The patent applies different oxide thickness requirements to different functional regions: the tunnel oxide adjacent to the control gate/floating gate is made thicker (50-200 nm) to withstand program/erase cycles, while other oxide layers in the logic device can remain thin for high integration. This localized differentiation allows both high device integration and robust non-volatile memory operation
3Ease of manufacture
If different types of semiconductor devices are fabricated on the same substrate, then packaging cost is reduced, but processing complexity increases due to different layer requirements
Solution Approach 1:
The non-volatile memory cell is designed to use the same processing steps and layers as the logic device, making the fabrication process universal for both device types. The control gate serves dual purposes, allowing both logic and memory functions to be created through identical manufacturing sequences, thereby reducing packaging costs without increasing processing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reprogrammable non-volatile memory devices with shared processing steps and layers, reducing costs and increasing device yield by minimizing additional processing requirements, while maintaining adequate program/erase cycle capability for applications requiring limited cycles.
Implementation Method 1
The floating gate is formed on the insulation layer and is electrically insulated from the surface of the semiconductor body by the insulation layer
Implementation Method 2
Flash memory operates on the principle of using a MOS transistor with a floating gate to selectively store a charge. The operation of the channel in the MOSFET will change upon whether a charge is stored on the floating gate
Implementation Method 3
The effect on the conductivity of the MOSFET channel is detectible and thus the state of the memory cell, either a logical 1 or 0, is detectable by read logic
Data Source
AI summary
A non-volatile memory device and method for manufacture and programing which does not require a control gate for the programing or erasure of the device. The memory device is comprised of two wells with the opposite conductivity type of the semiconductor body. In one of the wells is a source and drain well of the same conductivity type as of the body. A oxide is formed on the surface of the body on which a floating gate is formed. Specific voltages are applied to the source, drain, first well and second well region to program, erase and read the memory device.