Nonvolatile Memory Fail Bit Accumulation for Write Speed
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Solution Overview
Problem
In nonvolatile semiconductor memory, the increasing number of fail bits due to smaller memory cell size and the need to control threshold distribution within a narrow range lead to repetitive write and verify operations, slowing down the write operation speed.
Innovation Solution
A nonvolatile semiconductor memory system with a memory cell array, sense amplifiers, detection circuits, and an accumulator that parallelly reads and accumulates fail bits across multiple sense amplifiers, allowing for efficient detection and transfer of fail bits to improve write operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase storage capacity, then storage density is improved, but the number of fail bits increases leading to more repetitions of write and verify operations
Solution Approach 1:
The memory cell array is divided into multiple blocks, and fail bit detection is performed independently for each block. This segmentation allows parallel processing of fail bit detection across different blocks, reducing the total time required despite the increased number of fail bits from smaller memory cells.
2Quantity of substance
If the number of bits per memory cell is increased to improve storage capacity, then storage density is improved, but threshold distribution control becomes more difficult requiring more write and verify repetitions
Solution Approach 1:
The patent replaces manual or sequential threshold control with an automated detection and control system. The fail bit detection circuit automatically identifies bits that failed to meet threshold requirements, and the control circuit systematically adjusts write conditions, eliminating the need for manual iterative control and reducing the number of repetitions required.
3Reliability
If the number of repetitions of write and verify is increased to ensure data integrity, then reliability is improved, but write operation speed decreases
Solution Approach 1:
The system performs preliminary fail bit detection after each write operation using dedicated detection circuits that quickly identify failed bits before full verification. This preliminary action allows the control circuit to focus subsequent write operations only on blocks with detected failures, reducing the total number of repetitions needed while maintaining data integrity.
Solution Approach 2:
The patent implements a feedback mechanism where fail bit detection results from each write-verify cycle are fed back to the control circuit. The control circuit uses this feedback information to adjust subsequent write operations, targeting only the specific blocks or cells that failed, thereby reducing redundant repetitions and improving overall write speed while maintaining reliability.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array including memory cells of a first unit in which read and write are parallelly performed, n (n is a natural number of not less than 2) sense amplifiers, n detection circuits corresponding to the n sense amplifiers, an accumulator configured to divide the first unit data read from the memory cell array into z (z is a natural number) second unit data and accumulate a fail bit for which the write is incomplete for the second unit data, and a control circuit configured to control an operation of detecting the fail bit after the write.